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1.发明申请CONTINUOUS TIME LINEAR EQUALIZATION FOR CURRENT-MODE LOGIC WITH TRANSFORMER 有权具有变压器的电流模式逻辑的连续时间线性均衡公开(公告)号：US20160294582A1
公开(公告)日：2016-10-06
申请号：US15074530
申请日：2016-03-18
Applicant: INPHI CORPORATION
Inventor： Parmanand MISHRA , Steffen NIELSEN , Michael S. HARWOOD
CPC classification number: H04L25/03057 , H03K19/094 , H04L25/0272 , H04L25/03885
Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。
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2.发明申请CONTINUOUS TIME LINEAR EQUALIZATION FOR CURRENT-MODE LOGIC WITH TRANSFORMER 有权具有变压器的电流模式逻辑的连续时间线性均衡公开(公告)号：US20170078120A1
公开(公告)日：2017-03-16
申请号：US15359338
申请日：2016-11-22
Applicant: INPHI CORPORATION
Inventor： Parmanand MISHRA , Steffen NIELSEN , Michael S. HARWOOD
CPC classification number: H04L25/03057 , H03K19/094 , H04L25/0272 , H04L25/03885
Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.
Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。
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