公开(公告)号：US20200287040A1

公开(公告)日：2020-09-10

申请号：US16297516

申请日：2019-03-08

申请人： INSIDE SECURE

发明人： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234

摘要： A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.

公开(公告)号：US20180341737A1

公开(公告)日：2018-11-29

申请号：US16056268

申请日：2018-08-06

申请人： INSIDE SECURE

发明人： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC分类号： G06F17/50 ,  H01L27/02 ,  G06F21/14 ,  H01L27/118 ,  H03K19/177

摘要： The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.

公开(公告)号：US10923596B2

公开(公告)日：2021-02-16

申请号：US16297516

申请日：2019-03-08

申请人： INSIDE SECURE

发明人： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

摘要： A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.

公开(公告)号：US20200311222A1

公开(公告)日：2020-10-01

申请号：US16364056

申请日：2019-03-25

申请人： INSIDE SECURE

发明人： Bryan J. Wang ,  Lap Wai Chow ,  James P. Baukus ,  Ronald P. Cocchi

IPC分类号： G06F17/50

摘要： A method and an apparatus for camouflaging an application specific integrated circuit are disclosed. The ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function. In one embodiment, the method comprises accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising a sequential logic component and a virtual camouflage component, generating a logical description of the circuit, the logical description of the circuit comprising a logical description of the virtual camouflage component, and replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component.

公开(公告)号：US20190258766A1

公开(公告)日：2019-08-22

申请号：US16333589

申请日：2017-09-19

申请人： INSIDE SECURE

发明人： Bryan J. Wang ,  Lap Wai Chow ,  Ronald P. Cocchi ,  James P. Baukus

IPC分类号： G06F17/50 ,  H01L23/00

摘要： A method and apparatus for obfuscating at least a portion of an integrated circuit is disclosed. In one embodiment, the method comprises computing a number of observable points (COP) for each net of the portion of the integrated circuit, computing a selection weight (WS) for each net, and selecting one or more nets for insertion of at least one protection element based on the computed selection weights (WS).

公开(公告)号：US10817638B2

公开(公告)日：2020-10-27

申请号：US16364056

申请日：2019-03-25

申请人： INSIDE SECURE

发明人： Bryan J. Wang ,  Lap Wai Chow ,  James P. Baukus ,  Ronald P. Cocchi

IPC分类号： G06F30/39 ,  G06F30/392 ,  G06F30/398

摘要： A method and an apparatus for camouflaging an application specific integrated circuit are disclosed. The ASIC comprises a circuit comprising a plurality of interconnected functional logic cells performing a logical function. In one embodiment, the method comprises accepting a coded description of the circuit, wherein the coded description describes the circuit in terms of components comprising a sequential logic component and a virtual camouflage component, generating a logical description of the circuit, the logical description of the circuit comprising a logical description of the virtual camouflage component, and replacing, in the logical description of the circuit, the logical description of the virtual camouflage component with a logical description of a functionally equivalent technology-dependent camouflaged component.

公开(公告)号：US20200285719A1

公开(公告)日：2020-09-10

申请号：US16297511

申请日：2019-03-08

申请人： INSIDE SECURE

发明人： Bryan J. Wang ,  Lap Wai Chow ,  James P. Baukus ,  Ronald P. Cocchi

IPC分类号： G06F21/14 ,  H03K19/20 ,  G01R31/3185 ,  G11C7/10

摘要： A camouflaged shift registers and method for producing same is disclosed. In one embodiment, the camouflaged shift register comprises a plurality of serially coupled flip-flops, each of the flip-flops comprising a logic output communicatively coupled to an input of a serially adjacent next flip-flop and a camouflage element communicatively coupled between the logic output of a first flip-flop of the plurality of flip-flops and the input of a second flip-flop of the plurality of flip-flops serially adjacent to the first flip-flop, wherein the camouflage element has a physical layout mimicking a first function but performs a second function different from the first function.

公开(公告)号：US10691860B2

公开(公告)日：2020-06-23

申请号：US16056268

申请日：2018-08-06

申请人： INSIDE SECURE

发明人： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC分类号： G06F17/50 ,  G06F30/392 ,  H01L27/02 ,  G06F21/14 ,  H03K19/17736 ,  H01L27/118 ,  G06F30/39 ,  G06F30/394 ,  G06F30/34

摘要： The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.