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公开(公告)号：US20190087716A1
公开(公告)日：2019-03-21
申请号：US16079525
申请日：2016-08-09
Inventor： Zidong DU , Qi GUO , Tianshi CHEN , Yunji CHEN
Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.
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Patent Agency Ranking
公开(公告)号：US20180321944A1
公开(公告)日：2018-11-08
申请号：US15773970
申请日：2016-06-17
Inventor： Daofu LIU , Shengyuan ZHOU , Yunji CHEN
IPC: G06F9/30
CPC classification number: G06F9/30105 , G06F9/30021 , G06F9/3012 , G06F17/30
Abstract: The present disclosure relates to a data ranking apparatus that comprises: a register group for storing K pieces of temporarily ranked maximum or minimum data in a data ranking process, the register group comprises a plurality of registers connected in parallel, and two adjacent registers unidirectionally transmit data from a low level to a high level; a comparator group, which comprises a plurality of comparators connected to the registers on a one-to-one basis, compares the size relationship among a plurality of pieces of input data, and outputs the data of larger or smaller value to the corresponding registers; and a control circuit generating a plurality of flag bits applying to the registers, wherein the flag bits are used to judge whether the registers receive data transmitted from corresponding comparators or lower-level registers, and judge whether the registers transmit data to high level registers.
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公开(公告)号：US20190018766A1
公开(公告)日：2019-01-17
申请号：US16070735
申请日：2016-08-09
Inventor： Qi GUO , Tianshi CHEN , Yunji CHEN
IPC: G06F12/02
Abstract: The present disclosure may include a method that comprises: partitioning data on an on-chip and/or an off-chip storage medium into different data blocks according to a pre-determined data partitioning principle, wherein data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block; and a data indexing step for successively loading different data blocks to at least one on-chip processing unit according a pre-determined ordinal relation of a replacement policy, wherein the repeated data in a loaded data block being subjected to on-chip repetitive addressing. Data with a reuse distance less than a pre-determined distance threshold value is partitioned into the same data block, and the data partitioned into the same data block can be loaded on a chip once for storage, and is then used as many times as possible, so that the access is more efficient.
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公开(公告)号：US20180321912A1
公开(公告)日：2018-11-08
申请号：US15773973
申请日：2016-06-17
Inventor： Zhen LI , Shaoli LIU , Shijin ZHANG , Tao LUO , Cheng QIAN , Yunji CHEN , Tianshi CHEN
CPC classification number: G06F7/5095 , G06F7/50 , G06F16/2246
Abstract: The present disclosure provides a data accumulation device and method, and a digital signal processing device. The device comprises: an accumulation tree module for accumulating input data in the form of a binary tree structure and outputting accumulated result data; a register module including a plurality of groups of registers and used for registering intermediate data generated by the accumulation tree module during an accumulation process and the accumulated result data; and a control circuit for generating a data gating signal to control the accumulation tree module to filter the input data not required to be accumulated, and generating a flag signal to perform the following control: selecting a result obtained after adding one or more of intermediate data stored in the register to the accumulated result as output data, or directly selecting the accumulated result as output data. Thus, a plurality of groups of input data can be rapidly accumulated to a group of sums in a clock cycle. At the same time, the accumulation device can flexibly select to simultaneously accumulate some data of the plurality of of input data by means of a control signal.
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5.发明申请公开(公告)号：US20200272595A1
公开(公告)日：2020-08-27
申请号：US15781039
申请日：2016-06-17
Inventor： Dong HAN , Tao LUO , Shaoli LIU , Shijin ZHANG , Yunji CHEN
IPC: G06F15/78 , G06F17/16 , G06F16/901
Abstract: An example device comprises a central node for receiving vector data returned by leaf nodes, a plurality of leaf nodes for calculating and shifting the vector data, and forwarder modules comprising a local cache structure and a data processing component, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes; the central node is individually in communication connection with each group of leaf nodes by means of the forwarder modules; a communication structure constituted by each group of leaf nodes has self-similarity; the plurality of leaf nodes are in communication connection with the central node in a complete M-way tree approach by means of the forwarder modules of multiple levels; each of the leaf nodes comprises a setting bit.
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6.发明申请公开(公告)号：US20180375789A1
公开(公告)日：2018-12-27
申请号：US15781686
申请日：2016-06-17
Inventor： Huiying LAN , Tao LUO , Shaoli LIU , Shijin ZHANG , Yunji CHEN
IPC: H04L12/911 , G06F15/173 , H04L12/44 , H04L12/755
Abstract: A communication structure comprises: a central node that is a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; a plurality of leaf nodes that are communication data nodes of the network-on-chip and used for transmitting the communication data to the central node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes, the central node is individually in communication connection with each group of leaf nodes by means of the forwarder modules, the communication structure is a fractal-tree structure, the communication structure constituted by each group of leaf nodes has self-similarity, and the forwarder modules comprises a central forwarder module, leaf forwarder modules, and intermediate forwarder modules.
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