公开(公告)号：US20210158753A1

公开(公告)日：2021-05-27

申请号：US17053992

申请日：2018-08-02

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Di GENG ,  Yue SU ,  Ling LI ,  Nianduan LU ,  Ming LIU

IPC分类号： G09G3/3233 ,  G09G3/3291

摘要： A pixel compensation circuit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and an organic light-emitting diode, each of the first transistor to the sixth transistor including a drain, a source and a gate.

公开(公告)号：US20190006584A1

公开(公告)日：2019-01-03

申请号：US16064120

申请日：2016-08-12

申请人： INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

发明人： Nianduan LU ,  Pengxiao SUN ,  Ling LI ,  Ming IIU ,  Qi LIU ,  Hangbing LV ,  Shibing LONG

IPC分类号： H01L45/00

摘要： A method for improving endurance of 3D integrated resistive switching memory, comprising: Step 1: Calculating the temperature distribution in the integrated array by the 3D Fourier heat conduction equation; Step 2, selecting heat transfer mode; Step 3: selecting an appropriate array structure; Step 4: analyzing the influence of integration degree on temperature in the array; Step 5: evaluating the endurance performance in the array; and Step 6: changing the array parameters according to the evaluation result to improve the endurance performance. According to the method of the present invention, based on the thermal transmission mode in the 3D integrated resistive switching device, a suitable 3D integrated array is selected to analyze the influence of the integration degree on the device temperature so as to evaluate and improve the endurance of the 3D integrated resistive switching device.