公开(公告)号：US20220019365A1

公开(公告)日：2022-01-20

申请号：US17390441

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Divya NARAYANAN ,  Jawad B. KHAN ,  Michael D. NELSON ,  Akshay G. PETHE

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

公开(公告)号：US20190243571A1

公开(公告)日：2019-08-08

申请号：US16383490

申请日：2019-04-12

Applicant: INTEL CORPORATION

Inventor： Divya NARAYANAN ,  Jawad B. KHAN ,  Michael D. NELSON ,  Akshay G. PETHE

IPC: G06F3/06

CPC classification number: G06F3/0646 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0683

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.