公开(公告)号：US20210007235A1

公开(公告)日：2021-01-07

申请号：US16932635

申请日：2020-07-17

Applicant: Intel Corporation

Inventor： Michael D. NELSON ,  Jawad B. KHAN ,  Randall K. WEBB

IPC: H05K7/14 ,  G06F1/20 ,  G06F1/18 ,  H05K7/20

Abstract: Data storage system connectors are described for a parallel array of dense memory cards that allow high airflow. In one example, a connector has a horizontal plane board having a plurality of memory connectors aligned in a row and a plurality of external interfaces, a plurality of memory cards, each having an edge connector at one end of the memory card to connect to a respective memory connector of the board, each memory card extending horizontally parallel to each other memory card and extending vertically and orthogonally from the board, and a plurality of interface connectors each to connect an edge connector to a respective board connector, the interface connectors extending horizontally from the one end of the memory cards and vertically to the respective plane board connector.

公开(公告)号：US20220019365A1

公开(公告)日：2022-01-20

申请号：US17390441

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Divya NARAYANAN ,  Jawad B. KHAN ,  Michael D. NELSON ,  Akshay G. PETHE

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

公开(公告)号：US20190286197A1

公开(公告)日：2019-09-19

申请号：US16343741

申请日：2016-10-26

Applicant: INTEL CORPORATION

Inventor： Jawad B. KHAN ,  Andrew Warrack MORNING-SMITH ,  John HUNG ,  Michael D. NELSON ,  Craig J. JAHNE

IPC: G06F1/18 ,  H05K1/02 ,  G06F1/20 ,  H05K7/20 ,  H05K1/18 ,  H05K7/14 ,  F21V8/00

Abstract: An integrated electronic card front EMI cage and latch is described that is suitable for use in a data storage system. In an example a latch module for an electronic component housing has a latch housing having an arm with an attachment point to fasten the latch housing to an end of the housing and an EMI cage having a front body and a plurality of fingers extending from the front body, the front body being held to the end of the housing by the latch housing and the fingers being configured to be outside an exterior of the housing on at least two sides of the housing to block electromagnetic interference from passing along the at least two sides of the housing.

公开(公告)号：US20190243571A1

公开(公告)日：2019-08-08

申请号：US16383490

申请日：2019-04-12

Applicant: INTEL CORPORATION

Inventor： Divya NARAYANAN ,  Jawad B. KHAN ,  Michael D. NELSON ,  Akshay G. PETHE

IPC: G06F3/06

CPC classification number: G06F3/0646 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0683

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.