公开(公告)号：US20190019793A1

公开(公告)日：2019-01-17

申请号：US16080914

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Daniel H, MORRIS ,  Uygar E. AVCI ,  Ian A. YOUNG

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78

Abstract: One embodiment provides an apparatus. The apparatus includes a first transistor and a second transistor. The first transistor includes a first drain, a first source coupled to the first drain by a first channel, and a first gate stack comprising a plurality of layers. The second transistor includes a second drain, a second source coupled to the second drain by a second channel, and a second gate stack comprising a plurality of layers. Each gate stack includes a work function material layer to optimize a threshold voltage variation between the transistors.