公开(公告)号：US20240232096A9

公开(公告)日：2024-07-11

申请号：US18279029

申请日：2021-03-25

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Phillip Lantz ,  Rajesh Sankaran ,  David Hansen ,  Evgeny V. Voevodin ,  Andrew Anderson ,  Lizhen You ,  Xin Zhou ,  Nikhil Talpallikar

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.

公开(公告)号：US10969980B2

公开(公告)日：2021-04-06

申请号：US16367944

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： David Hansen ,  Ashok Raj

IPC: G06F12/00 ,  G06F3/06

Abstract: A processor includes a processing core; a filter register to store a first permissions filter; and a memory management unit (MMU), coupled to the processing core, the filter register and a first peripheral device associated with the first permissions filter, wherein the MMU comprises a logic circuit to manage a shared page table comprising entries corresponding to the processing core and the first peripheral device, wherein the logic circuit is to; receive a memory access request for a first page of memory from the first peripheral device; determine whether the set of permission bits of the first entry match a first combination of bits of the first permissions filter; grant the memory access request if the set of permission bits match the first combination of bits of the first permissions filter; and cause a page fault if the set of permission bits do not matching the first combination of bits.

公开(公告)号：US20240134803A1

公开(公告)日：2024-04-25

申请号：US18279029

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Sanjay Kumar ,  Phillip Lantz ,  Rajesh Sankaran ,  David Hansen ,  Evgeny V. Voevodin ,  Andrew Anderson ,  Lizhen You ,  Xin Zhou ,  Nikhil Talpallikar

IPC: G06F12/1009

CPC classification number: G06F12/1009

Abstract: An embodiment of an integrated circuit may comprise an array of hardware counters, and circuitry communicatively coupled to the array of hardware counters, the circuitry to count accesses to one or more selected pages of a memory with the array of hardware counters. Other embodiments are disclosed and claimed.

公开(公告)号：US20200004677A1

公开(公告)日：2020-01-02

申请号：US16020444

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Amin Firoozshahian ,  Omid Azizi ,  Chandan Egbert ,  David Hansen ,  Andreas Kleen ,  Mahesh Maddury ,  Mahesh Madhav ,  Alexandre Solomatnikov ,  John Peter Stevenson

IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06

Abstract: Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.

公开(公告)号：US11556341B2

公开(公告)日：2023-01-17

申请号：US17341068

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

公开(公告)号：US20220012059A1

公开(公告)日：2022-01-13

申请号：US17341068

申请日：2021-06-07

Applicant: Intel Corporation

Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

公开(公告)号：US11029957B1

公开(公告)日：2021-06-08

申请号：US16833478

申请日：2020-03-27

Applicant: INTEL CORPORATION

Inventor： Ravi Sahita ,  Deepak Gupta ,  Vedvyas Shanbhogue ,  David Hansen ,  Jason W. Brandt ,  Joseph Nuzman ,  Mingwei Zhang

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

Abstract: Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.

公开(公告)号：US20200310665A1

公开(公告)日：2020-10-01

申请号：US16367944

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： David Hansen ,  Ashok Raj

IPC: G06F3/06

Abstract: A processor includes a processing core; a filter register to store a first permissions filter; and a memory management unit (MMU), coupled to the processing core, the filter register and a first peripheral device associated with the first permissions filter, wherein the MMU comprises a logic circuit to manage a shared page table comprising entries corresponding to the processing core and the first peripheral device, wherein the logic circuit is to; receive a memory access request for a first page of memory from the first peripheral device; determine whether the set of permission bits of the first entry match a first combination of bits of the first permissions filter; grant the memory access request if the set of permission bits match the first combination of bits of the first permissions filter; and cause a page fault if the set of permission bits do not matching the first combination of bits.