公开(公告)号：US20190042220A1

公开(公告)日：2019-02-07

申请号：US15922059

申请日：2018-03-15

Applicant: Intel Corporation

Inventor： Satish K. Guggilla ,  Prasad Battini ,  Dmitry Budanov ,  John Ng

IPC: G06F8/41 ,  G06F17/30

CPC classification number: G06F8/4434 ,  G06F16/2272

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a field of a data structure as a candidate for a size reduction, perform a runtime analysis on the field, and reduce the size of the field based on the runtime analysis. Other embodiments are disclosed and claimed.

公开(公告)号：US10678524B2

公开(公告)日：2020-06-09

申请号：US15922059

申请日：2018-03-15

Applicant: Intel Corporation

Inventor： Satish K. Guggilla ,  Prasad Battini ,  Dmitry Budanov ,  John Ng

IPC: G06F8/41 ,  G06F16/22

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a field of a data structure as a candidate for a size reduction, perform a runtime analysis on the field, and reduce the size of the field based on the runtime analysis. Other embodiments are disclosed and claimed.

公开(公告)号：US20190042221A1

公开(公告)日：2019-02-07

申请号：US15972345

申请日：2018-05-07

Applicant: INTEL CORPORATION

Inventor： Rakesh Krishnaiyer ,  Konstantin Bobrovskii ,  Dmitry Budanov

IPC: G06F8/41

Abstract: Logic may transform a target code to partition data automatically and/or autonomously based on a memory constraint associated with a resource such as a target device. Logic may identify a tag in the code to identify a task, wherein the task comprises at least one loop, the loop to process data elements in one or more arrays. Logic may automatically generate instructions to determine one or more partitions for the at least one loop to partition data elements, accessed by one or more memory access instructions for the one or more arrays within the at least one loop, based on a memory constraint, the memory constraint to identify an amount of memory available for allocation to process the task. Logic may determine one or more iteration space blocks for the parallel loops, determine memory windows for each block, copy data into and out of constrained memory, and transform array accesses.