公开(公告)号：US20180061122A1

公开(公告)日：2018-03-01

申请号：US15252004

申请日：2016-08-30

Applicant: INTEL CORPORATION

Inventor： FRANZ PETRIK CLARBERG

IPC: G06T15/80 ,  G06T1/20 ,  G06F3/01 ,  G06T1/60 ,  G06T15/50 ,  G06T15/04 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06F3/013 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T15/04 ,  G06T15/503

Abstract: A mechanism is described for facilitating multi-resolution deferred shading using texel shaders in computing environments. A method of embodiments, as described herein, includes facilitating computation of shading rate in a first pass in a graphics pipeline, where the shading rate relates to a plurality of pixels. The method may further include facilitating texel shading operations in a second pass using the shading rate, where the first pass is performed separate from and prior to the second pass.

公开(公告)号：US20170287207A1

公开(公告)日：2017-10-05

申请号：US15089168

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： FRANZ PETRIK CLARBERG

IPC: G06T15/30 ,  G06T15/00 ,  G06T15/40

CPC classification number: G06T15/30 ,  G06T11/40 ,  G06T15/005 ,  G06T15/40

Abstract: An apparatus and method are described for conservative rasterization. For example, one embodiment of a graphics processing apparatus comprises: an edge tagging circuit to identify edges of two or more triangles forming a convex polygon as inner edges or non-inner edges; and a rasterizer to responsively perform rasterization of the two or more triangles using a first edge processing circuit for inner edges and a second edge processing circuit for non-inner edges.

公开(公告)号：US20190172254A1

公开(公告)日：2019-06-06

申请号：US16248713

申请日：2019-01-15

Applicant: Intel Corporation

Inventor： Jon N. Hasselgren ,  Jacob J. Munkberg ,  FRANZ PETRIK CLARBERG ,  Tomas G. AKENINE-MOLLER

IPC: G06T15/40 ,  G06T15/00 ,  G06T15/80 ,  G06T1/60

Abstract: A method for improving performance of generation of digitally represented graphics. The method comprises: receiving a first representation of a base primitive; providing a set of instructions associated with vertex position determination; executing said retrieved set of instructions on said first representation of said base primitive using bounded arithmetic for providing a second representation of said base primitive, and subjecting said second representation of said base primitive to a culling process. A corresponding apparatus and computer program product are also presented.