公开(公告)号：US20180374951A1

公开(公告)日：2018-12-27

申请号：US15777707

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACOB M. JENSEN ,  DANIEL B. AUBERTINE ,  CHANDRA S. MOHAPATRA

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.