公开(公告)号：US20180374951A1

公开(公告)日：2018-12-27

申请号：US15777707

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACOB M. JENSEN ,  DANIEL B. AUBERTINE ,  CHANDRA S. MOHAPATRA

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Tensile strain is applied to a channel region of a transistor by depositing an amorphous SixGe1-x-yCy alloy in at least one of a source and a drain (S/D) region of the transistors. The amorphous SixGe1-x-yCy alloy is crystallized, thus reducing the unit volume of the alloy. This volume reduction in at least one of the source and the drain region applies strain to a connected channel region. This strain improves electron mobility in the channel. Dopant activation in the source and drain locations is recovered during conversion from amorphous to crystalline structure. Presence of high carbon concentrations reduces dopant diffusion from the source and drain locations into the channel region. The techniques may be employed with respect to both planar and non-planar (e.g., FinFET and nanowire) transistors.

公开(公告)号：US20160260802A1

公开(公告)日：2016-09-08

申请号：US15155806

申请日：2016-05-16

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KELIN J. KUHN ,  SEIYON KIM ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/0676 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7855 ,  H01L29/78696

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20180158841A1

公开(公告)日：2018-06-07

申请号：US15576393

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  TAHIR GHANI ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  CHANDRA S. MOHAPATRA ,  KARTHIK JAMBUNATHAN ,  GILBERT DEWEY ,  WILLY RACHMADY

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

公开(公告)号：US20150228772A1

公开(公告)日：2015-08-13

申请号：US14690615

申请日：2015-04-20

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  KELIN J. KUHN ,  SEIYON KIM ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE

IPC: H01L29/775 ,  H01L29/66

CPC classification number: H01L29/0676 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7855 ,  H01L29/78696

Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Abstract translation: 公开了用于定制纳米线晶体管器件以提供同一集成电路管芯内的不同范围的通道配置和/或材料系统的技术。 根据一个示例性实施例，除去牺牲翅片并用适合于给定应用的任意组合和应变的定制材料堆叠代替。 在一种这样的情况下，第一组牺牲散热片中的每一个凹陷或以其它方式移除并被p型层堆叠代替，并且第二组牺牲散热片中的每一个凹进或以其它方式移除， 类型层堆栈。 p型层堆栈可以完全独立于n型层堆栈的过程，反之亦然。 使用本文提供的技术可实现许多其它电路配置和设备变化。

公开(公告)号：US20180247939A1

公开(公告)日：2018-08-30

申请号：US15754871

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PRASHANT MAJHI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  DANIEL B. AUBERTINE ,  HEIDI M. MEYER ,  KARTHIK JAMBUNATHAN ,  GOPINATH BHIMARASETTI

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

公开(公告)号：US20180019170A1

公开(公告)日：2018-01-18

申请号：US15668288

申请日：2017-08-03

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  DANIEL B. AUBERTINE ,  ANAND S. MURTHY ,  GAURAV THAREJA ,  TAHIR GHANI

IPC: H01L21/8238 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/1054

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20170133376A1

公开(公告)日：2017-05-11

申请号：US15115825

申请日：2014-03-24

Applicant: Intel Corporation

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  SUBHASH M. JOSHI

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/3065

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).