公开(公告)号：US10021408B2

公开(公告)日：2018-07-10

申请号：US15661539

申请日：2017-07-27

Applicant: INTEL CORPORATION

Inventor： Zhichong Chen ,  Jinfeng Zhou ,  Jianbin He ,  Liu Yang ,  Qiang Li

IPC: H04N19/433 ,  H04N19/51

CPC classification number: H04N19/433 ,  H04N19/51

Abstract: The invention provides a video codec. In one embodiment, the video codec is coupled to an outer memory storing a reference frame, and comprises an interface circuit, an in-chip memory, a motion estimation circuit, and a controller. The interface circuit obtains in-chip data from the reference frame stored in the outer memory. The in-chip memory stores the in-chip data. The motion estimation circuit retrieves search window data from the in-chip data with a search window, and performs a motion estimation process on a current macroblock according to the search-window data. The controller shifts the location of the search window when the current macroblock is shifted, marks a macroblock shifted out from the search window as an empty macroblock, and controls the interface circuit to obtain an updated macroblock for replacing the empty macroblock in the in-chip memory from the reference frame stored in the outer memory.

公开(公告)号：US10469868B2

公开(公告)日：2019-11-05

申请号：US14818886

申请日：2015-08-05

Applicant: Intel Corporation

Inventor： Yinglai Xi ,  Qiang Li ,  Jumei Li ,  Jianbin He ,  Jinfeng Zhou ,  Zhichong Chen ,  Liu Yang ,  Dong Li

IPC: H04N19/547 ,  H04N19/117 ,  H04N19/122 ,  H04N19/56 ,  H04N19/50 ,  H04N19/82 ,  H04N19/433 ,  H04N19/533 ,  H04N19/523

Abstract: An in-loop filtering acceleration circuit applied in a video codec system supporting the H.264 standard and the VC-1 standard is provided. The circuit includes multiple one-dimensional (1D) filters configured to perform a filtering process; and a filter selection unit configured to select one of the 1D filters according to the value of the boundary strength to perform the filtering processing to the reconstructed macroblock. The in-loop filtering acceleration circuit further divides the reconstructed macroblock into multiple 8×8 blocks and multiple 4×4 blocks, performs the filtering process to horizontal edges of the 8×8 blocks the reconstructed macroblock row by row from bottom to top, and performs the filtering process to horizontal edges of the 4×4 blocks row by row from top to bottom.

公开(公告)号：US09961354B2

公开(公告)日：2018-05-01

申请号：US15584572

申请日：2017-05-02

Applicant: INTEL CORPORATION

Inventor： Zhichong Chen ,  Jinfeng Zhou ,  Jianbin He ,  Liu Yang ,  Qiang Li

IPC: H04N19/433 ,  H04N19/51

CPC classification number: H04N19/433 ,  H04N19/51

Abstract: The invention provides a video codec. In one embodiment, the video codec is coupled to an outer memory storing a reference frame, and comprises an interface circuit, an in-chip memory, a motion estimation circuit, and a controller. The interface circuit obtains in-chip data from the reference frame stored in the outer memory. The in-chip memory stores the in-chip data. The motion estimation circuit retrieves search window data from the in-chip data with a search window, and performs a motion estimation process on a current macroblock according to the search-window data. The controller shifts the location of the search window when the current macroblock is shifted, marks a macroblock shifted out from the search window as an empty macroblock, and controls the interface circuit to obtain an updated macroblock for replacing the empty macroblock in the in-chip memory from the reference frame stored in the outer memory.