公开(公告)号：US09918088B2

公开(公告)日：2018-03-13

申请号：US14458524

申请日：2014-08-13

Applicant: Intel Corporation

Inventor： Qiang Li ,  Jumei Li ,  Yinglai Xi ,  Fei Su

IPC: H04N19/12 ,  H04N19/124 ,  H04N19/157 ,  H04N19/179 ,  H04N19/42 ,  H04N19/156 ,  H04N19/436

CPC classification number: H04N19/12 ,  H04N19/124 ,  H04N19/156 ,  H04N19/157 ,  H04N19/179 ,  H04N19/42 ,  H04N19/436

Abstract: A transform and inverse transform circuit is provided. The transform and inverse transform circuit includes: at least one quantization and inverse quantization circuit, including at least one quantization and inverse quantization unit, wherein each quantization and inverse quantization unit includes a plurality of first coefficients, and each quantization and inverse quantization unit performs quantization or inverse quantization on one of multiple ways of inputting data; and at least one one-dimensional transform circuit, coupled to the quantization and inverse quantization circuit, wherein the one-dimensional transform circuit includes a plurality of second coefficients, wherein the one-dimensional transform circuit performs one-dimensional transform on the inputting data processed by the quantization and inverse quantization circuit, wherein the plurality of first coefficients and the plurality of second coefficients are set up based on a video codec standard.

公开(公告)号：US10469868B2

公开(公告)日：2019-11-05

申请号：US14818886

申请日：2015-08-05

Applicant: Intel Corporation

Inventor： Yinglai Xi ,  Qiang Li ,  Jumei Li ,  Jianbin He ,  Jinfeng Zhou ,  Zhichong Chen ,  Liu Yang ,  Dong Li

IPC: H04N19/547 ,  H04N19/117 ,  H04N19/122 ,  H04N19/56 ,  H04N19/50 ,  H04N19/82 ,  H04N19/433 ,  H04N19/533 ,  H04N19/523

Abstract: An in-loop filtering acceleration circuit applied in a video codec system supporting the H.264 standard and the VC-1 standard is provided. The circuit includes multiple one-dimensional (1D) filters configured to perform a filtering process; and a filter selection unit configured to select one of the 1D filters according to the value of the boundary strength to perform the filtering processing to the reconstructed macroblock. The in-loop filtering acceleration circuit further divides the reconstructed macroblock into multiple 8×8 blocks and multiple 4×4 blocks, performs the filtering process to horizontal edges of the 8×8 blocks the reconstructed macroblock row by row from bottom to top, and performs the filtering process to horizontal edges of the 4×4 blocks row by row from top to bottom.

公开(公告)号：US09918079B2

公开(公告)日：2018-03-13

申请号：US13888635

申请日：2013-05-07

Applicant: Intel Corporation

Inventor： Yinglai Xi ,  Qiang Li ,  Zhichong Chen ,  Jumei Li

IPC: H04N19/43 ,  H04N19/105 ,  H04N19/44 ,  H04N19/80 ,  H04N19/523

CPC classification number: H04N19/43 ,  H04N19/44 ,  H04N19/523 ,  H04N19/80

Abstract: An electronic device for motion compensation is provided. The electronic device has a processing unit configured to perform a decoding program on a video bitstream to output decoding data, wherein the decoding data has a plurality of inter-prediction macroblocks, and the processing unit further generates a plurality of first pixel interpolation values according to the inter-prediction macroblocks which are smaller than a predetermined macroblock size. A motion compensation acceleration circuit is configured to generate a plurality of second pixel interpolation values according to the inter-prediction macroblocks which are larger than or equal to the predetermined macroblocks size, and generate a plurality of reconstructed macroblocks according to the first pixel interpolation values, the second pixel interpolation values, and a plurality of corresponding residue values.