公开(公告)号：US20190026149A1

公开(公告)日：2019-01-24

申请号：US16066652

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： Yong JIANG ,  Yuanyuan LI ,  Jianghong DU ,  Kuilin CHEN ,  Thomas A. TETZLAFF

IPC: G06F9/48 ,  G06T1/20 ,  G06F9/52 ,  G06F9/30

Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.