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公开(公告)号:US20180341526A1
公开(公告)日:2018-11-29
申请号:US15775249
申请日:2015-12-24
Applicant: INTEL CORPORATION
Inventor: Yuanyuan LI , Yong JIANG , Linghyi KONG
Abstract: A mechanism is described for facilitating efficient communication and data processing across clusters of computing machines in a heterogeneous computing environment. A method includes detecting a request for processing of data using a programming framework and a programming model; facilitating interfacing between the programming framework and the programming model, wherein interfacing includes merging the programming model into the programming framework, wherein interfacing further includes integrating the programming framework with a distribution framework hosting the programming model; and calling on the distribution framework to schedule processing of a plurality of jobs based on the request.
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公开(公告)号:US20220091934A1
公开(公告)日:2022-03-24
申请号:US17544085
申请日:2021-12-07
Applicant: Intel Corporation
Inventor: Lei CHEN , Liyang LING , Xiaodong QIU , Yong JIANG
Abstract: An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.
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公开(公告)号:US20210248087A1
公开(公告)日:2021-08-12
申请号:US17054762
申请日:2018-09-27
Applicant: Intel Corporation
Inventor: Yanjie PAN , Yong JIANG , Yuanyuan LI , Yong ZHANG
IPC: G06F12/123 , G06F12/0893
Abstract: Systems, methods, and computer-readable media are provided for variable precision first in, first out (FIFO) buffers (VPFB) that dynamically changes the amount of data to be stored in the VPFB based on a current amount of data stored in the VPFB and/or based on a current amount of available memory space of the VPFB. The currently unavailable memory space (or the current available memory space) is used to select the size of a next data block to be stored in the VPFB. Other embodiments are disclosed and/or claimed.
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公开(公告)号:US20210334127A1
公开(公告)日:2021-10-28
申请号:US17197304
申请日:2021-03-10
Applicant: Intel Corporation
Inventor: Yong JIANG , Yuanyuan Li , Jianghong Du , Kuilin Chen , Thomas A. Tetzlaff
Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.
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公开(公告)号:US20190026149A1
公开(公告)日:2019-01-24
申请号:US16066652
申请日:2016-04-01
Applicant: INTEL CORPORATION
Inventor: Yong JIANG , Yuanyuan LI , Jianghong DU , Kuilin CHEN , Thomas A. TETZLAFF
Abstract: Embodiments described herein provide a system, method, and apparatus to accelerate reduce operations in a graphics processor. One embodiment provides an apparatus including one or more processors, the one or more processors including a first logic unit to perform a merged write, barrier, and read operation in response to a barrier synchronization request from a set of threads in a work group, synchronize the set of threads, and report a result of an operation specified in association with the barrier synchronization request.
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公开(公告)号:US20180084410A1
公开(公告)日:2018-03-22
申请号:US15797445
申请日:2017-10-30
Applicant: INTEL CORPORATION
Inventor: Xiaoyong PAN , Justin LIPMAN , Yuhuan HUANG , Yong JIANG , Ke DING , Dzinh J. NGUYEN , Robert A. COLBY
CPC classification number: H04W12/02 , H04B17/318 , H04W4/025 , H04W4/029 , H04W12/00503 , H04W12/08 , H04W72/1247 , H04W88/08
Abstract: Technologies for location privacy management include a mobile computing device to determine whether an application is authorized to obtain the location of the mobile computing device based on a determined location and location access policy of the mobile computing device. The location access policy includes policy rules that identify whether the application is authorized to obtain the location of the mobile computing device. If the mobile computing device determines that the application is not authorized to obtain the location of the mobile computing device, the mobile computing device blocks the application from obtaining the location.
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公开(公告)号:US20160255497A1
公开(公告)日:2016-09-01
申请号:US14129641
申请日:2013-07-19
Applicant: INTEL CORPORATION
Inventor: Xiaoyong PAN , Justin LIPMAN , Yuhuan HUANG , Yong JIANG , Ke DING , Dzinh J. NGUYEN , Robert A. COLBY
IPC: H04W12/02 , H04W72/12 , H04W4/02 , H04B17/318
CPC classification number: H04W12/02 , H04B17/318 , H04W4/02 , H04W4/025 , H04W12/08 , H04W72/1247 , H04W88/08
Abstract: Technologies for location privacy management include a mobile computing device to determine whether an application is authorized to obtain the location of the mobile computing device based on a determined location and location access policy of the mobile computing device. The location access policy includes policy rules that identify whether the application is authorized to obtain the location of the mobile computing device. If the mobile computing device determines that the application is not authorized to obtain the location of the mobile computing device, the mobile computing device blocks the application from obtaining the location.
Abstract translation: 用于位置隐私管理的技术包括移动计算设备,用于基于所确定的移动计算设备的位置和位置访问策略来确定应用是否被授权获得移动计算设备的位置。 位置访问策略包括标识应用是否被授权获得移动计算设备的位置的策略规则。 如果移动计算设备确定应用程序未被授权获得移动计算设备的位置,则移动计算设备阻止应用程序获取该位置。
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公开(公告)号:US20240168717A1
公开(公告)日:2024-05-23
申请号:US18083366
申请日:2022-12-16
Applicant: Intel Corporation
Inventor: Yong JIANG , Chengxi WU , Ruiqi YANG , Xiaodong QIU , Xiaoxi CHEN , Zilan LIANG , Xiaoxuan YANG
CPC classification number: G06F7/5443 , G06F7/49942
Abstract: A processor of an aspect is to perform operations corresponding to an unsigned integer multiply-accumulate instruction. The unsigned integer multiply-accumulate instruction is to indicate a first unsigned integer, a second unsigned integer, a first register that is have a third unsigned integer, and a second register. The operations include to multiply the first unsigned integer and the second unsigned integer to generate a product and add the product and the third unsigned integer to generate a sum. The operations also include to store a first portion of the sum in the second register. The first portion of the sum includes M least significant bits of the sum. The operations also include to store a second portion of the sum in the first register. The second portion of the sum includes all bits of the sum that are more significant than the M least significant bits. Other processors are also disclosed.
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