公开(公告)号：US20210325855A1

公开(公告)日：2021-10-21

申请号：US17359184

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rita Wouhaybi ,  Samudyatha C. Kaira ,  Rajesh Poornachandran ,  Francesc Guim Bernat ,  Kevin Stanton

IPC: G05B19/4155 ,  G06N20/00

Abstract: Methods and apparatus for Time-Sensitive Networking Coordinated Transfer Learning in industrial settings are disclosed. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to cause performance of an operation by a first machine according to a first configuration, process a performance metric of the performance of the operation by the first machine to determine whether the performance metric is within a threshold range, and in response to a determination that the performance metric is not within the threshold range, cause performance of the operation by a second machine according to a second configuration different from the first configuration.

公开(公告)号：US20220014532A1

公开(公告)日：2022-01-13

申请号：US17483723

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Javier Perez-Ramirez ,  Mikhail Galeev ,  Marcio Juliato ,  Christopher Gutierrez ,  Dave Cavalcanti ,  Manoj Sastry ,  Kevin Stanton ,  Vuk Lesi

IPC: H04L29/06

Abstract: Systems and methods to detect attacks on the clocks of devices. In time sensitive networks are described. Particularly, the disclosed systems and methods provide detection and mitigation of timing synchronization attacks based on key performance indicators related to the protecting transmission windows in data streams of the time sensitive networks.

公开(公告)号：US12228909B2

公开(公告)日：2025-02-18

申请号：US17359184

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Rita Wouhaybi ,  Samudyatha C. Kaira ,  Rajesh Poornachandran ,  Francesc Guim Bernat ,  Kevin Stanton

IPC: G05B19/4155 ,  G06N20/00

Abstract: Methods and apparatus for Time-Sensitive Networking Coordinated Transfer Learning in industrial settings are disclosed. An example apparatus includes at least one memory, instructions in the apparatus, and processor circuitry to execute the instructions to cause performance of an operation by a first machine according to a first configuration, process a performance metric of the performance of the operation by the first machine to determine whether the performance metric is within a threshold range, and in response to a determination that the performance metric is not within the threshold range, cause performance of the operation by a second machine according to a second configuration different from the first configuration.

公开(公告)号：US12081561B2

公开(公告)日：2024-09-03

申请号：US17483723

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Javier Perez-Ramirez ,  Mikhail Galeev ,  Marcio Juliato ,  Christopher Gutierrez ,  Dave Cavalcanti ,  Manoj Sastry ,  Kevin Stanton ,  Vuk Lesi

IPC: H04L9/40

CPC classification number: H04L63/1416 ,  H04L63/1425

Abstract: Systems and methods to detect attacks on the clocks of devices. In time sensitive networks are described. Particularly, the disclosed systems and methods provide detection and mitigation of timing synchronization attacks based on key performance indicators related to the protecting transmission windows in data streams of the time sensitive networks.

公开(公告)号：US20220123849A1

公开(公告)日：2022-04-21

申请号：US17561398

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： David McCall ,  Kevin Stanton

IPC: H04J3/06 ,  H04W56/00

Abstract: The present disclosure provides techniques for measuring and compensating for clock drift errors in time-aware networks and time-sensitive applications, where a time-aware system (TAS) measures clock drift, and compensates for the measured clock drift, and makes predictions of future clock drift values based on history and other physical measurements. Existing messages used for measuring link delay and/or used for time synchronization can be used for frequency measurement (and thus clock drift measurement), and this measured drift can be applied as a correction factor whenever synchronization is determined and/or used. The predicted clock drift rate can be based on various probability distributions including linear, Kalman filters, and/or others. Other embodiments may be described and/or claimed.

公开(公告)号：US10931989B2

公开(公告)日：2021-02-23

申请号：US15829612

申请日：2017-12-01

Applicant: INTEL CORPORATION

Inventor： Sangeeta Ghangam ,  Kevin Stanton ,  Eric Auzas ,  Christopher Hall

IPC: H04N21/24 ,  H04N21/242 ,  H04L7/00 ,  H04N5/04 ,  H04J3/06 ,  H04N21/43 ,  H04N21/6332

Abstract: Systems and methods of generating a synchronized media content presentation using a plurality of media output systems communicably coupled to a respective plurality of network connected platforms are provided. A first network connected platform receives an IEEE 802.1AS master timing signal generated by “Grand Master” timing circuitry disposed in a second network connected platform. IEEE 802.1AS application service circuitry disposed in the first network connected platform determines an offset between a local timing signal and the receive master timing signal. Talker circuitry disposed in the first network connected platform synchronizes a media content presentation to the master timing signal and communicates a media/master timing signal synchronization signal to each of the network connected platforms. The media/master timing signal synchronization signal includes data representative of a media start location and a media start time referenced to the master timing signal.