公开(公告)号：US20160344379A9

公开(公告)日：2016-11-24

申请号：US14929154

申请日：2015-10-30

Applicant: INTEL CORPORATION

Inventor： Mark NEIDENGARD ,  Vaughn GROSSNICKLE ,  Nasser KURD ,  Jeffrey KRIEGER

IPC: H03K5/156 ,  H03K3/03

CPC classification number: H03K5/1565 ,  H03K3/0315

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.

Abstract translation: 这里描述了用于重新合成时钟信号的装置，方法和系统。 该装置包括：第一逻辑单元，用于检测输入时钟信号的上升沿，并且用于基于检测到的输入时钟信号的上升沿产生输出时钟信号的上升沿，所述输入时钟信号具有非50 占空比的百分之一和第一期; 以及第二逻辑单元，用于根据检测到的输入时钟信号的上升沿计算输出时钟信号的下降沿，输出时钟信号的下降沿接近第一周期的一半。

公开(公告)号：US20180212608A1

公开(公告)日：2018-07-26

申请号：US15414408

申请日：2017-01-24

Applicant: Intel Corporation

Inventor： Mark NEIDENGARD

IPC: H03K23/58 ,  H03K3/037

CPC classification number: H03K23/588 ,  G09G5/00 ,  G09G2310/0264

Abstract: An apparatus is described. The apparatus includes a counter circuit having ordered state element circuits where a respective clock input of a state element circuit is fed by a data output of a preceding lower ordered bit state element. The counter circuit also being programmable to enable different amounts to be counted by the counter circuit, wherein respective reload values for the amounts are received at the state elements as a respective asynchronous set or reset.

公开(公告)号：US20160056807A1

公开(公告)日：2016-02-25

申请号：US14929154

申请日：2015-10-30

Applicant: INTEL CORPORATION

Inventor： Mark NEIDENGARD ,  Vaughn GROSSNICKLE ,  Nasser KURD ,  Jeffrey KRIEGER

IPC: H03K5/156 ,  H03K3/03

CPC classification number: H03K5/1565 ,  H03K3/0315

Abstract: Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an input clock signal and for generating a rising edge of an output clock signal based on the detected rising edge of the input clock signal, the input clock signal having a non-50% duty cycle and a first period; and a second logic unit to compute a falling edge of the output clock signal according to the detected rising edge of the input clock signal, the falling edge of the output clock signal being near half of the first period.