公开(公告)号：US20180107453A1

公开(公告)日：2018-04-19

申请号：US15696036

申请日：2017-09-05

Applicant: Intel Corporation

Inventor： T.J. O'DWYER ,  PIERRE LAURENT

IPC: G06F7/523

CPC classification number: G06F7/523

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.

公开(公告)号：US20180004662A1

公开(公告)日：2018-01-04

申请号：US15201348

申请日：2016-07-01

Applicant: INTEL CORPORATION

Inventor： ANDREW CUNNINGHAM ,  MARK D. GRAY ,  ALEXANDER LECKEY ,  CHRIS MACNAMARA ,  STEPHEN T. PALERMO ,  PIERRE LAURENT ,  NIALL D. MCDONNELL ,  TOMASZ KANTECKI ,  PATRICK FLEMING

IPC: G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/06 ,  G06F12/0831 ,  G06F12/126 ,  G06F2212/283 ,  G06F2212/621

Abstract: An input/output (I/O) device arranged to receive an information element including a payload, determine control information from the information element, classify the information element based on the control information, and issue a write to one of a plurality of computer-readable media based on the classification of the information element, the write to cause the payload to be written to the one of the plurality of computer-readable media.

公开(公告)号：US20160274866A1

公开(公告)日：2016-09-22

申请号：US14664669

申请日：2015-03-20

Applicant: Intel Corporation

Inventor： T.J. O'DWYER ,  PIERRE LAURENT

IPC: G06F7/533 ,  G06F7/72

CPC classification number: G06F7/533 ,  G06F7/723

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.

Abstract translation: 一个实施例提供一种系统。 该系统包括一个用于存储操作数的寄存器; 乘数 以及优化器逻辑，用于启动平方/乘法级以对操作数进行操作，在完成平方/乘法级之前启动减少级，并确定是否发生进位传播。

公开(公告)号：US20180097843A1

公开(公告)日：2018-04-05

申请号：US15282564

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： MICHAEL HINGSTON MCLAUGHLIN BURSELL ,  STEPHEN T. PALERMO ,  CHRIS MACNAMARA ,  PIERRE LAURENT ,  JOHN J. BROWNE

IPC: H04L29/06

CPC classification number: H04L63/20 ,  H04L63/0876 ,  H04L63/1408 ,  H04L63/1433

Abstract: A round-robin network security system implemented by a number of peer devices included in a plurality of networked peer devices. The round-robin security system permits the rotation of the system security controller among at least a portion of the peer devices. Each of the peer devices uses a defined trust assessment ruleset to determine whether the system security controller is trusted/trustworthy. An untrusted system security controller peer device is replaced by another of the peer devices selected by the peer devices. The current system security controller peer device transfers system threat information and security risk information collected from the peer devices to the new system security controller elected by the peer devices.

公开(公告)号：US20160283195A1

公开(公告)日：2016-09-29

申请号：US14668349

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： T.J. O'DWYER ,  PIERRE LAURENT

IPC: G06F5/00 ,  G06F7/523

CPC classification number: G06F7/523

Abstract: One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a first reduction stage to operate on the operand, initiate a second reduction stage prior to completion of the first reduction stage, and determine whether a carry propagation has occurred.

Abstract translation: 一个实施例提供一种系统。 该系统包括一个用于存储操作数的寄存器; 乘数 以及优化器逻辑，用于启动第一减少级以对所述操作数进行操作，在所述第一减少级完成之前启动第二级还原级，并确定是否发生进位传播。