公开(公告)号：US10115721B2

公开(公告)日：2018-10-30

申请号：US15167006

申请日：2016-05-27

Applicant: INTEL CORPORATION

Inventor： Walid M. Hafez ,  Peter J Vandervoorn ,  Chia-Hong Jan

IPC: H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/161

Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.