公开(公告)号：US20160321834A1

公开(公告)日：2016-11-03

申请号：US14961755

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： RAHUL P. SATHE ,  TIM FOLEY

IPC: G06T15/00 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/60 ,  G06T2200/28

Abstract: An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache to store a multiplicity of processed vertices of the mesh. The apparatus may further include a processor circuit, and a vertex manager for execution on the processor circuit to read a reference bitstream comprising a multiplicity of bitstream entries, each bitstream entry corresponding to an index entry of the index stream, and to remove a processed vertex from the vertex cache when a value of the reference bitstream entry corresponding to the processed vertex is equal to a defined value.

公开(公告)号：US20190066256A1

公开(公告)日：2019-02-28

申请号：US16170597

申请日：2018-10-25

Applicant: INTEL CORPORATION

Inventor： SAURABH SHARMA ,  ABHISHEK VENKATESH ,  TRAVIS T. SCHLUESSLER ,  THOMAS F. RAOUX ,  RAHUL P. SATHE ,  JON HASSELGREN

IPC: G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06F8/41

Abstract: Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.