公开(公告)号：US20160179673A1

公开(公告)日：2016-06-23

申请号：US14582148

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： RAMACHARAN SUNDARARAMAN ,  TRACEY L. GUSTAFSON ,  ROBERT J. SAFRANEK

IPC: G06F12/08

CPC classification number: G06F12/0831 ,  G06F12/0833 ,  G06F2212/621 ,  Y02D10/13

Abstract: Methods and apparatus relating to techniques for Cross-Die Interface (CDI) snoop and/or go (or completion) message ordering are described. In one embodiment, the order of a snoop message and a completion message are determined based at least on status of two bits. The snoop and completion messages are exchanged between a first integrated circuit die and a second integrated circuit die. The first integrated circuit die and the second integrated circuit die are coupled through a first interface and a second interface and the snoop message and the completion message are exchanged over at least one of the first interface and the second interface. Other embodiments are also disclosed.

Abstract translation: 描述了与跨模接口（CDI）窥探和/或去（或完成）消息排序技术相关的方法和装置。 在一个实施例中，至少基于两位的状态来确定窥探消息和完成消息的顺序。 窥探和完成消息在第一集成电路管芯和第二集成电路管芯之间交换。 第一集成电路管芯和第二集成电路管芯通过第一接口和第二接口耦合，并且窥探消息和完成消息通过第一接口和第二接口中的至少一个进行交换。 还公开了其他实施例。

公开(公告)号：US20190007310A1

公开(公告)日：2019-01-03

申请号：US15639393

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： DEBENDRA DAS SHARMA ,  MICHELLE C. JEN ,  MARK S. MYERS ,  DON SOLTIS ,  RAMACHARAN SUNDARARAMAN ,  STEPHEN R. VAN DOREN ,  MAHESH WAGH

IPC: H04L12/781 ,  H04L29/06 ,  H04L12/931

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

公开(公告)号：US20180173628A1

公开(公告)日：2018-06-21

申请号：US15835384

申请日：2017-12-07

Applicant: Intel Corporation

Inventor： CHUNHUI ZHANG ,  GEORGE Z. CHRYSOS ,  EDWARD T. GROCHOWSKI ,  RAMACHARAN SUNDARARAMAN ,  CHUNG-LUN CHAN ,  FEDERICO ARDANAZ

IPC: G06F12/0842 ,  G06F12/0817 ,  G06F9/38 ,  G06F12/0831

CPC classification number: G06F12/0842 ,  G06F9/38 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0835 ,  G06F2212/1016 ,  G06F2212/283 ,  G06F2212/621

Abstract: Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated with the memory and the operations associated with one or more of the functional units may be determined. A first ordering may be created for the operations associated with the memory. Furthermore, a second ordering may be created for the operations associated with one or more of the functional units based on the determined dependency and the first operating of the operations associated with the memory.