公开(公告)号：US20170286210A1

公开(公告)日：2017-10-05

申请号：US15087797

申请日：2016-03-31

Applicant: INTEL CORPORATION

Inventor： Theodros YIGZAW ,  Ashok RAJ ,  Robert SWANSON ,  Mohan J. KUMAR

IPC: G06F11/07 ,  G06F12/08

CPC classification number: G06F11/0793 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1064 ,  G06F12/0804 ,  G06F12/0811 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7201

Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.