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1.发明公开公开(公告)号：US20240241778A1
公开(公告)日：2024-07-18
申请号：US18562237
申请日：2021-12-13
Applicant: Intel Corporation
Inventor： Shen ZHOU , Cong LI , Kuljit S. BAINS , Ugonna ECHERUO , Reza E. DAFTARI , Theodros YIGZAW , Mariusz ORIOL
IPC: G06F11/07
CPC classification number: G06F11/073 , G06F11/079 , G06F11/0793
Abstract: A system (204) can respond to detection of an uncorrectable error (UE) (254) in memory (246) based on fault-aware analysis. The fault-aware analysis enables the system (204) to generate a determination of a specific hardware element of the memory (246) that caused the detected UE (254). In response to detection of a UE (254), the system (204) can correlate a hardware configuration (256) of the memory (246) device with historical data indicating memory (246) faults for hardware elements of the hardware configuration (256). Based on a determination of the specific component that likely caused the UE (254), the system (204) can issue a corrective action for the specific hardware element based on the determination.
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Patent Agency Ranking
公开(公告)号：US20240211344A1
公开(公告)日：2024-06-27
申请号：US18025868
申请日：2020-09-26
Applicant: Intel Corporation
Inventor： Kuljit S. BAINS , Kjersten E. CRISS , Rajat AGARWAL , Omar AVELAR SUAREZ , Subhankar PANDA , Theodros YIGZAW , Rebecca Z. LOOP , John G. HOLM , Gaurav PORWAL
CPC classification number: G06F11/106 , G11C29/02
Abstract: A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.
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3.发明公开公开(公告)号：US20240061741A1
公开(公告)日：2024-02-22
申请号：US18268956
申请日：2020-12-26
Applicant: Intel Corporation
Inventor： Rajat AGARWAL , Hsing-Min CHEN , Wei P. CHEN , Wei WU , Jing LING , Kuljit S. BAINS , Kjersten E. CRISS , Deep K. BUCH , Theodros YIGZAW , John G. HOLM , Andrew M. RUDOFF , Vaibhav SINGH , Sreenivas MANDAVA
IPC: G06F11/10
CPC classification number: G06F11/10
Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.
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公开(公告)号：US20230205626A1
公开(公告)日：2023-06-29
申请号：US18116785
申请日：2023-03-02
Applicant: Intel Corporation
CPC classification number: G06F11/1064 , G06F11/0787 , G06F11/076
Abstract: Multilevel memory error management techniques can improve system performance, availability, and reliability by preventing future accesses to faulty near memory locations. According to examples described herein, multilevel memory error management techniques enable proactively offlining far memory locations mapped to a faulty near memory location before additional faults are encountered, and/or maintaining a faulty near memory location list to enable bypassing the faulty near memory location to prevent future errors.
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公开(公告)号：US20220350500A1
公开(公告)日：2022-11-03
申请号：US17855688
申请日：2022-06-30
Applicant: Intel Corporation
Inventor： Wei P. CHEN , Theodros YIGZAW , Sarathy JAYAKUMAR , Anthony LUCK , Deep K. BUCH , Rajat AGARWAL , Kuljit S. BAINS , John G. HOLM , Brent CHARTRAND , Keith KLAYMAN
IPC: G06F3/06
Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.
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6.发明申请公开(公告)号：US20170286210A1
公开(公告)日：2017-10-05
申请号：US15087797
申请日：2016-03-31
Applicant: INTEL CORPORATION
Inventor： Theodros YIGZAW , Ashok RAJ , Robert SWANSON , Mohan J. KUMAR
CPC classification number: G06F11/0793 , G06F11/073 , G06F11/0751 , G06F11/079 , G06F11/1064 , G06F12/0804 , G06F12/0811 , G06F2212/1021 , G06F2212/1032 , G06F2212/214 , G06F2212/22 , G06F2212/7201
Abstract: An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.
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