公开(公告)号：US10373948B2

公开(公告)日：2019-08-06

申请号：US15203296

申请日：2016-07-06

Applicant: Intel Corporation

Inventor： Christopher P. Mozak ,  Victor Zia ,  Gabriel J. Thompson

IPC: H02H9/04 ,  H01L27/02

Abstract: Some embodiments include apparatus and methods using a first transistor coupled between a node and a supply node, a second transistor coupled between the node and a ground node, an electrostatic discharge (ESD) protection unit including a diode coupled between the node and an additional node, and a transistor coupled between the additional node and the supply node.

公开(公告)号：US20170242068A1

公开(公告)日：2017-08-24

申请号：US15051571

申请日：2016-02-23

Applicant: INTEL CORPORATION

Inventor： Huy Le ,  Mona Mayeh ,  Victor Zia ,  Robert F. Kwasnick

IPC: G01R31/28

CPC classification number: G01R31/2858

Abstract: Described is an apparatus which comprises: a first array of reliability monitors including first and second reliability monitors, wherein the first and second reliability monitors include first and second switches and first and second conductors, wherein the first and second switches are coupled to first and second conductors, respectively; and first and second comparators coupled to the first and second switches, respectively. Described is an apparatus which comprises: a conductor formed on a metal layer; a switch having a source terminal coupled to the conductor, and a drain terminal coupled to a power supply node, wherein the switch is controllable by a controller; and a comparator having a first input coupled to the power supply node and to the switch, wherein the comparator includes a second input coupled to an adjustable reference.