公开(公告)号：US20210004334A1

公开(公告)日：2021-01-07

申请号：US16772765

申请日：2018-03-28

Applicant: INTEL CORPORATION

Inventor： Kun TIAN ,  Xiao ZHENG ,  Ashok RAJ ,  Sanjay KUMAR ,  Rajesh SANKARAN

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

公开(公告)号：US20190220301A1

公开(公告)日：2019-07-18

申请号：US16328062

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Xiao ZHENG ,  Yao Zu DONG ,  Kun TIAN

IPC: G06F9/455 ,  G06F12/02

CPC classification number: G06F9/45558 ,  G06F12/0292 ,  G06F12/1009 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/50 ,  G06F2212/651 ,  G06F2212/657

Abstract: An apparatus and method are described for implementing a hybrid layer of address mapping for an IOMMU implementation. For example, one embodiment of a graphics processing apparatus comprises: virtualization circuitry to implement a virtualized execution environment in which a plurality of guest virtual machines (VMs) are to execute and share execution resources of the graphics processing apparatus; an input/output (I/O) memory management unit (IOMMU) to couple the VMs to one or more I/O devices; a hybrid layer address mapping (HLAM) module to combine entries from a per-process graphics translation table (PPGTT) with entries from a global graphics translation table (GGTT) into a first integrated page table, the first integrated page table mapping PPGTT guest page numbers (GPNs) to host page numbers (HPNs) and mapping GGTT virtual GPNs to HPNs; the HLAM to transform a GGTT GPN into a virtual GPN usable to access a corresponding HPN within the first integrated page table in response to a GGTT read/write operation generated by a first guest virtual machine (VM).