公开(公告)号：US20200218471A1

公开(公告)日：2020-07-09

申请号：US16638694

申请日：2017-09-25

Applicant: INTEL CORPORATION

Inventor： Zhi Yong CHEN ,  Zhiqiang QIN ,  Xueyan WANG ,  Fang YUAN

IPC: G06F3/06

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

公开(公告)号：US20220129205A1

公开(公告)日：2022-04-28

申请号：US17568956

申请日：2022-01-05

Applicant: INTEL CORPORATION

Inventor： Zhi Yong CHEN ,  Zhiqiang QIN ,  Xueyan WANG ,  Fang YUAN

IPC: G06F3/06

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.