公开(公告)号：US20230263077A1

公开(公告)日：2023-08-17

申请号：US18164125

申请日：2023-02-03

Applicant: International Business Machines Corporation

Inventor： TAKASHI ANDO ,  HIROYUKI MIYAZOE ,  EDUARD ALBERT CARTIER ,  BABAR KHAN ,  YOUNGSEOK KIM ,  DEXIN KONG ,  SOON-CHEON SEO ,  JOEL P. DE SOUZA

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/041 ,  H10B63/80 ,  H10N70/021 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833

Abstract: Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a memory stack over the metal interconnect electrode. The memory stack includes a plurality of layers that includes a top electrode, a plasma-treated bottom electrode, and a dielectric layer between the top electrode and the plasma-treated bottom electrode. The plasma-treated bottom electrode includes a portion of a blanket bottom electrode layer. The plasma-treated bottom electrode further includes a current-conducting filament characteristic that results from a charge particle treatment applied to the blanket bottom electrode while a top surface of the blanket bottom electrode is exposed.

公开(公告)号：US20210391536A1

公开(公告)日：2021-12-16

申请号：US16898527

申请日：2020-06-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： TAKASHI ANDO ,  HIROYUKI MIYAZOE ,  EDUARD ALBERT CARTIER ,  BABAR KHAN ,  YOUNGSEOK KIM ,  DEXIN KONG ,  SOON-CHEON SEO ,  JOEL P. DE SOUZA

IPC: H01L45/00 ,  H01L27/24

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.