公开(公告)号：US20180232292A1

公开(公告)日：2018-08-16

申请号：US15432584

申请日：2017-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Erez Barak ,  Oz D. Hershkovitz ,  Gilad Merran ,  Eyal Naor

IPC: G06F11/26 ,  G06F11/22 ,  G06F17/50

CPC classification number: G06F11/26 ,  G06F11/2236 ,  G06F17/5022 ,  G06F2217/68

Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.

公开(公告)号：US10324815B2

公开(公告)日：2019-06-18

申请号：US15432584

申请日：2017-02-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Erez Barak ,  Oz D. Hershkovitz ,  Gilad Merran ,  Eyal Naor

IPC: G06F11/00 ,  G06F11/26 ,  G06F11/22 ,  G06F17/50

Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.