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公开(公告)号：US20220246564A1
公开(公告)日：2022-08-04
申请号：US17681019
申请日：2022-02-25
发明人： Guilian Gao , Javier A. DeLaCruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, JR. , Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号： H01L23/00
摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
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公开(公告)号：US11296044B2
公开(公告)日：2022-04-05
申请号：US16553535
申请日：2019-08-28
发明人： Guilian Gao , Javier A. Delacruz , Shaowu Huang , Liang Wang , Gaius Gillman Fountain, Jr. , Rajesh Katkar , Cyprian Emeka Uzoh
IPC分类号： H01L23/00
摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.
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公开(公告)号：US10784191B2
公开(公告)日：2020-09-22
申请号：US15940273
申请日：2018-03-29
发明人： Shaowu Huang , Belgacem Haba , Javier A. DeLaCruz
IPC分类号： H01L23/522 , H01L23/498 , H01L23/00 , H01L25/065 , H01L23/538 , H03H7/01 , H03H1/00
摘要： A stacked and electrically interconnected structure is disclosed. The structure can comprise a first element and a second element directly bonded to the first element along a bonding interface without an intervening adhesive. A filter circuit can be integrally formed between the first and second elements along the bonding interface.
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公开(公告)号：US11169326B2
公开(公告)日：2021-11-09
申请号：US16247262
申请日：2019-01-14
发明人： Shaowu Huang , Javier A. Delacruz , Liang Wang , Guilian Gao
摘要： Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers. An example wafer-level process fabricates running waveguides, optical routing, and direct-bonded optical interconnects for silicon photonics and optoelectronics packages when two wafers are joined.
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公开(公告)号：US10658313B2
公开(公告)日：2020-05-19
申请号：US16189804
申请日：2018-11-13
发明人： Javier A. Delacruz , Rajesh Katkar , Shaowu Huang , Gaius Gillman Fountain, Jr. , Liang Wang , Laura Wills Mirkarimi
IPC分类号： H01L23/00 , H01L21/768 , H01L23/48 , H01L25/065 , H01L25/00
摘要： Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.
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公开(公告)号：US10446487B2
公开(公告)日：2019-10-15
申请号：US15709309
申请日：2017-09-19
发明人： Shaowu Huang , Javier DeLaCruz
IPC分类号： H01L23/522 , H01L23/00 , H01L23/64 , H01L25/065 , H01L23/498 , H01L25/18 , H03H7/06
摘要： A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.
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公开(公告)号：US20190198407A1
公开(公告)日：2019-06-27
申请号：US16212471
申请日：2018-12-06
发明人： Shaowu Huang , Javier A. DeLaCruz , Liang Wang , Rajesh Katkar , Belgacem Haba
CPC分类号： H01L23/10 , H01L23/66 , H01L2224/48091 , H01L2924/1616 , H01L2924/181
摘要： An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.
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公开(公告)号：US11417576B2
公开(公告)日：2022-08-16
申请号：US16678058
申请日：2019-11-08
发明人： Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh , Shaowu Huang , Guilian Gao , Ilyas Mohammed
摘要： Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
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公开(公告)号：US20210134689A1
公开(公告)日：2021-05-06
申请号：US17146304
申请日：2021-01-11
发明人： Shaowu Huang , Javier A. DeLaCruz , Liang Wang , Rajesh Katkar , Belgacem Haba
摘要： An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.
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公开(公告)号：US10508030B2
公开(公告)日：2019-12-17
申请号：US15920759
申请日：2018-03-14
发明人： Rajesh Katkar , Liang Wang , Cyprian Emeka Uzoh , Shaowu Huang , Guilian Gao , Ilyas Mohammed
摘要： Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.
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