STABILIZED ENTANGLING OPERATIONS IN A QUANTUM COMPUTING SYSTEM

    公开(公告)号:US20230334116A1

    公开(公告)日:2023-10-19

    申请号:US18118252

    申请日:2023-03-07

    Applicant: IONQ, INC.

    CPC classification number: G06F17/14 G06N10/40

    Abstract: A method of performing a quantum computation process includes computing first Fourier coefficients of a first pulse function of a first control pulse and second Fourier coefficients of a second pulse function of a second control pulse based on a condition for closure of phase space trajectories and a condition for stabilization of phase-space closure, and computing a first linear combination of the computed first Fourier coefficients and a second linear combination of the computed second Fourier coefficients based on a condition for non-zero degree of entanglement, a condition for stabilization of the degree of entanglement, and a condition for minimized power, applying the first control pulse having the computed first pulse function to a first trapped ion of a pair of trapped ions, and the second control pulse having the computed second pulse function to a second trapped ion of a pair of trapped ions.

    FAST TWO-QUBIT GATES ON A TRAPPED-ION QUANTUM COMPUTER

    公开(公告)号:US20240296360A1

    公开(公告)日:2024-09-05

    申请号:US17464595

    申请日:2021-09-01

    Applicant: IONQ, INC.

    CPC classification number: G06N10/20 G06N10/40

    Abstract: A method for performing an entangling operation between trapped ions in a quantum computer includes selecting an amount of infidelity that is allowed in an entangling operation between two trapped ions in a quantum computer, computing a pulse function of a pulse to be applied to each of the two trapped ions based on gate operation conditions and the selected amount of infidelity, generating the pulse based on the computed pulse function, and applying the generated pulse to each of the two trapped ions to perform the entangling operation between the two trapped ions.

    UNIVERSAL GATE PULSE FOR TWO-QUBIT GATES ON A TRAPPED-ION QUANTUM COMPUTER

    公开(公告)号:US20230401478A1

    公开(公告)日:2023-12-14

    申请号:US17971458

    申请日:2022-10-21

    Applicant: IONQ, INC.

    CPC classification number: G06N10/60

    Abstract: A method for performing at least a portion of a computational process includes computing a pulse function of a pulse to be applied to a first pair of trapped ions in a first ion chain based on a phase-space condition, wherein the phase-space condition is derived using equi-spaced synthetic frequencies in a frequency interval that includes a range set by a highest and a lowest motional mode frequency of the first ion chain, generating the pulse based on the computed pulse function, and applying the generated pulse to each of a second pair of trapped ions in a second ion chain to perform an entangling gate operation between the second pair of trapped ions in the second ion chain.

    Addition of Qubit States Using Entangled Quaternionic Roots of Single-Qubit Gates

    公开(公告)号:US20240169241A1

    公开(公告)日:2024-05-23

    申请号:US18175946

    申请日:2023-02-28

    Applicant: IonQ, Inc.

    CPC classification number: G06N10/40 G06F7/5525 G06N10/20

    Abstract: Systems and methods are provided for performing addition of qubit states using entangled quaternionic roots of single qubit gates. A method includes identifying a single qubit gate in a quantum circuit of a quantum computer, wherein the quantum circuit includes two summand qubits entangled with a third qubit that stores a measurable non-linear sum of the two summand qubits. The method includes mapping the single qubit gate to a representative gate that is phase-equivalent to the single qubit gate, mapping the representative gate to a unit quaternion, calculating an nth root of the unit quaternion, and mapping the nth root of the unit quaternion to a unitary matrix that represents a fractional single qubit gate. The method includes configuring the quantum circuit to include at least one fractional single qubit gate representing the unitary matrix in place of the single qubit gate for performing the addition.

    ERROR LIMITING PROTOCOL FOR THE CONSTRUCTION OF TWO-QUBIT GATES IN AN ION-TRAP QUANTUM COMPUTING SYSTEM

    公开(公告)号:US20250165845A1

    公开(公告)日:2025-05-22

    申请号:US18951410

    申请日:2024-11-18

    Applicant: IONQ, INC.

    Abstract: A method of performing a two-qubit gate operation includes computing, by a classical computer, a control pulse to be applied to a pair of trapped ions in a plurality of trapped ions in a quantum processor, each of the plurality of trapped ions having two frequency-separated states defining a qubit, wherein computing the control pulse comprises: computing a pulse function of the control pulse based on a phase-space closure condition and an auxiliary condition, and computing the pulse function of the control pulse further based on a gate angle condition, and applying, by a system controller, the control pulse, having the computed pulse function, to the pair of trapped ions.

    DEBUGGING OF QUANTUM CIRCUITS
    7.
    发明申请

    公开(公告)号:US20220383179A1

    公开(公告)日:2022-12-01

    申请号:US17746871

    申请日:2022-05-17

    Applicant: IONQ, INC.

    Abstract: A method of performing computation using a hybrid quantum-classical computing system including a classical computer, a system controller, and a quantum processor includes identifying a computational problem to be solved and a quantum algorithm to be used to solve the computational problem, detecting one or more faulty two-qubit gates among a plurality of two-qubit gates that can be applied to pairs of qubits in the quantum processor, compiling a computational task to solve the computational problem based on the quantum algorithm into a series of logic gates, including single-qubit gates and two-qubit gates that exclude the detected one or more faulty two-qubit gates, executing the series of logic gates on the quantum processor, measuring one or more of the qubits in the quantum processor, and outputting a solution to the identified computational problem derived from the measured results of the one or more of the qubits in the quantum processor.

    OPTIMAL CALIBRATION OF GATES IN A QUANTUM COMPUTING SYSTEM

    公开(公告)号:US20220206866A1

    公开(公告)日:2022-06-30

    申请号:US17531520

    申请日:2021-11-19

    Abstract: A method of performing a quantum computation process includes mapping, by a classical computer, logical qubits to physical qubits of a quantum processor so that quantum circuits are executable using the physical qubits of the quantum processor and a total infidelity of the plurality of quantum circuits is minimized, wherein each of the physical qubits comprise a trapped ion, and each of the plurality of quantum circuits comprises single-qubit gates and two-qubit gates within the plurality of the logical qubits, calibrating, by a system controller, two-qubit gates within a first plurality of pairs of physical qubits, such that infidelity of the two-qubit gates within the first plurality of pairs of physical qubit is lowered, executing the plurality of quantum circuits on the quantum processor, by applying laser pulses that each cause a single-qubit gate operation and a two-qubit gate operation in each of the plurality of quantum circuits on the plurality of physical qubits, measuring, by the system controller, population of qubit states of the physical qubits in the quantum processor after executing the plurality of quantum circuits on the quantum processor, and outputting, by the classical computer, the measured population of qubit states of the physical qubits as a result of the execution the plurality quantum circuits, wherein the result of the execution the plurality quantum circuits are configured to be displayed on a user interface, stored in a memory of the classical computer, or transferred to another computational device.

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