公开(公告)号：US20160283389A1

公开(公告)日：2016-09-29

申请号：US14671892

申请日：2015-03-27

申请人： ISRAEL DIAMAND ,  NIR MISGAV ,  ARAVINDH ANANTARAMAN ,  ZVIKA GREENFIELD

发明人： ISRAEL DIAMAND ,  NIR MISGAV ,  ARAVINDH ANANTARAMAN ,  ZVIKA GREENFIELD

IPC分类号： G06F12/08

CPC分类号： G06F12/0811

摘要： An apparatus is described that includes a memory controller having an interface to couple to a multi-level system memory. The memory controller also includes a coherency buffer and coherency services logic circuitry. The coherency buffer is to keep cache lines for which read and/or write requests have been received. The coherency services logic circuitry is coupled to the interface and the coherency buffer. The coherency services logic circuitry is to merge a cache line that has been evicted from a level of the multi-level system memory with another version of the cache line within the coherency buffer before writing the cache line back to a deeper level of the multi-level system memory if at least one of the following is true: the another version of said cache line is in a modified state; the memory controller has a pending write request for the cache line.

摘要翻译： 描述了一种装置，其包括具有耦合到多级系统存储器的接口的存储器控​​制器。 存储器控制器还包括一致性缓冲器和一致性服务逻辑电路。 一致性缓冲区是为了保持已经接收到读取和/或写入请求的高速缓存行。 一致性服务逻辑电路耦合到接口和一致性缓冲器。 一致性服务逻辑电路是将已经被逐出的高速缓存行与多级系统存储器的级别的高速缓存行中的高速缓存行的另一版本合并在一起， 如果以下至少一个为真，则级别系统存储器：所述高速缓存行的另一版本处于修改状态; 存储器控制器具有针对高速缓存行的待决写入请求。