公开(公告)号：US3770897A

公开(公告)日：1973-11-06

申请号：US3770897D

申请日：1971-12-06

Applicant: ITT

Inventor： HAUSSMANN R ,  EPSTEIN M

IPC: H04J3/06

CPC classification number: H04J3/0608

Abstract: A binary data transmission system employing a sending station and a receiving station with intermediate stations disposed therebetween in tandem. The binary data signal transmitted by such a system includes in a predetermined time division multiplex frame period M groups of time division multiplex channel data signals, each of the groups of channel signals having a normal sync signal. Each of the intermediate stations and the receiving station monitor the received and transmitted M groups of channel data signals on a time sequential basis. A frame synchronization system detects the lack of sync in any of the groups applied thereto on a time sequential basis and substitutes for the thusly detected erroneous group of channel signals dummy data signals including dummy sync signals. To prevent stations subsequent to the stations substituting the dummy data signals for erroneous normal data signals from providing an erroneous error indication and substitution of dummy data for error free normal data signal, the frame synchronization system detects, establishes and maintains sync of each monitored group of channel signals in response to either the normal sync signal or the dummy sync signal. The frame synchronization system provides a variable search time to establish the desired synchronization to either normal or dummy sync signals for each group of channel data signals coupled thereto.

Abstract translation: 一种采用发送站和接收站的二进制数据传输系统，其间设置有中间站。 由这种系统发送的二进制数据信号在预定的时分复用帧周期中包括多组时分复用信道数据信号，每组信道信号具有正常同步信号。 中间站和接收站中的每一个以时间顺序的方式监视接收和发送的M组信道数据信号。 帧同步系统在时间顺序的基础上检测到应用于其中的任何组中的同步性不足，并代替这样检测到的包括虚拟同步信号的伪数据信号的错误组的信道信号。 为了防止替代虚拟数据信号的站之后的站在错误的正常数据信号上提供错误的错误指示和用于无错误的正常数据信号的伪数据的替换，帧同步系统检测，建立并维持每个被监视的组的 响应于正常同步信号或伪同步信号的信道信号。 帧同步系统提供可变搜索时间，以便为与其耦合的每组信道数据信号建立与正常或伪同步信号的所需同步。

公开(公告)号：US3854102A

公开(公告)日：1974-12-10

申请号：US38707973

申请日：1973-08-09

Applicant: ITT

Inventor： SEIPEL A ,  DEUTSCH J ,  THOMPSON B ,  HAUSSMANN R

IPC: H03L7/185 ,  H03B3/04 ,  H03B19/00

CPC classification number: H03L7/185

Abstract: There is disclosed herein a dual frequency band frequency synthesizer employing a single phase locked loop to control the frequency of the output signal of a voltage controlled oscillator so as to provide signals having a selected frequency in a selected one of the two frequency bands with the frequency of the signals in each of the two frequency bands having different incremental frequency steps. The phase locked loop includes therein a programmable binary divider having a different range of division factors for each of the two frequency bands with the output of the programmable divider being coupled directly to the phase detector of the phase locked loop when the lower frequency band is selected and through a modulo-6 binary counter when the higher frequency bands is selected. The programmable binary divider is programmed by frequency setting switches which produces 9''s complement binary coded output for each of the selected decimal values. The coded decimal values of each of the frequency selecting switches are employed directly or through a decoding circuit to select the appropriate one of the two frequency bands, to program the programmable binary diver to the proper division factor for the frequency selected by the frequency setting switches and to bypass or incorporate the modulo-6 counter. The decoding circuit includes binary adders coupled to each of the switches intermediate the most significant switch and the least significant switch so as to add in digital form a first given constant value to the digital output of the switches when operating in the lower of the frequency bands and a second constant value in digital form when operating in the higher of the frequency bands so as to provide the proper division factor for the programmable binary divider for the frequency selected by the frequency setting switches. An automatic level control arrangement is also incorporated in the phase locked loop responding to the output signal in each frequency band to maintain a constant amplitude of output signal in each of the frequency bands.

公开(公告)号：US3742145A

公开(公告)日：1973-06-26

申请号：US3742145D

申请日：1972-04-17

Applicant: ITT

Inventor： CLARK J ,  HAUSSMANN R

IPC: H04J3/07 ,  H04J3/04

CPC classification number: H04J3/073

Abstract: There is described an asynchronous multiplexer and demultiplexer that operates on the basis of a stuff only technique. The multiplexer includes a different elastic store for each of the asynchronous input PCM data groups. Each of the elastic stores include a buffer register whose writing clock is synchronous with the asynchronous group input bit rate clock and a read clock which is synchronous with the bit rate of a synchronous data format employed for multiplexing the asynchronous group inputs. Each of the elastic stores produce a stuff request signal when the phase difference of the read and write clocks is equal to a given period, in numbers of bit periods. A common stuff control circuit samples the stuff requests and provides a control signal to inhibit the read clock to add or stuff a single stuff bit to the associated group data for each stuff request. Timing signals generated from a reference oscillator define the synchronous data format which includes 64 midframes within a superframe with each of the midframes including 15 subframes. Odd numbered ones of the subframes include 9 data bits and even numbered ones of the subframes include 8 data bits. The 9th data bit of the odd numbered subframes provide an overhead channel for transmitting digital voice orderwire, digital data orderwire, control words, a ''''zero'''' short sync bit, a ''''one'''' short sync bit and a long sync bit in each midframe. The bit assigned to the control words are employed to identify at the demultiplexer where the stuff bit has been added to the data format. The demultiplexer includes timing signal generators driven by the superframe rate recovered from the received data signal to provide the necessary timing signals to identify the supergroup frame, the midframe, the subframes and the data bits within the subframes. The timing signal generator in the demultiplexer is synchronized to the timing signal generators defining the data format in the multiplexer by a superframe recovery circuit responsive to both a short sync code and a pseudo-random long sync code. A common destuffing control is provided responsive to the code word identifying the presence or absence of a stuff bit to destuff the identified group data and thereby return the stuffed multiplexed group data to asynchronous group data as originally applied to the elastic stores of the multiplexer. The demultiplex includes for each asynchronous group data a different elastic store wherein the write clock is controlled by the recovered supergroup bit rate and the read clock is controlled at the group or midframe rate provided by the timing signal generators. The destuff control from the common destuff control circuit controls the write counter to cause destuffing of the associated one of the stuffed group data. A heterodyne type phase locked loop is employed in conjunction with each of the elastic stores to remove jitter from the destuffed group data.