LOWER PROCESSING RATE DECISION FEEDBACK EQUALIZER FOR HIGHER RATE CARRIER SIGNAL
    2.
    发明申请
    LOWER PROCESSING RATE DECISION FEEDBACK EQUALIZER FOR HIGHER RATE CARRIER SIGNAL 有权
    低速处理速率反馈平均值用于高速率载波信号

    公开(公告)号:US20090168865A1

    公开(公告)日:2009-07-02

    申请号:US11968075

    申请日:2007-12-31

    IPC分类号: H04L27/01

    CPC分类号: H04L25/03057

    摘要: Briefly, in accordance with one or more embodiments, parallel DFE processing may be utilized for single carrier systems that employ cyclic prefixes. The achieved parallelism allows working at contemporary clock rates that are significantly lower than the required sampling rate at high bandwidth systems such as 60 GHz transmissions.

    摘要翻译: 简而言之,根据一个或多个实施例,并行DFE处理可以用于采用循环前缀的单载波系统。 实现的并行性允许以当前时钟速率工作,这些时钟速率明显低于高带宽系统(如60 GHz传输)所需的采样率。

    Lower processing rate decision feedback equalizer for higher rate carrier signal
    4.
    发明授权
    Lower processing rate decision feedback equalizer for higher rate carrier signal 有权
    较低速率载波信号的较低处理速率判决反馈均衡器

    公开(公告)号:US07929598B2

    公开(公告)日:2011-04-19

    申请号:US11968075

    申请日:2007-12-31

    IPC分类号: H03H7/40 H03H7/30 H04B1/10

    CPC分类号: H04L25/03057

    摘要: Briefly, in accordance with one or more embodiments, parallel DFE processing may be utilized for single carrier systems that employ cyclic prefixes. The achieved parallelism allows working at contemporary clock rates that are significantly lower than the required sampling rate at high bandwidth systems such as 60 GHz transmissions.

    摘要翻译: 简而言之,根据一个或多个实施例,并行DFE处理可以用于采用循环前缀的单载波系统。 实现的并行性允许以当前时钟速率工作,这些时钟速率明显低于高带宽系统(如60 GHz传输)所需的采样率。

    Fast frequency-hopping transceiver and method
    5.
    发明授权
    Fast frequency-hopping transceiver and method 有权
    快速跳频收发器和方法

    公开(公告)号:US08457176B2

    公开(公告)日:2013-06-04

    申请号:US13309998

    申请日:2011-12-02

    IPC分类号: H04B1/713

    摘要: A fast frequency-hopping transceiver comprises a RF-unit arranged on a first chip, a base-band unit on a second chip, a bidirectional operable data and control interface arranged between said first and said second chip having at least one data line for data communication, at least one control line for controlling the data communication and at least one clock line for providing a clock signal, memory means implemented within said RF-unit containing all the required chip settings which are specific to a certain frequency of received and/or transmitted data being part of the intended hopping sequence. The transceiver also includes control means for programming said memory means during an initialization phase during a set-up of a communication link of said data communication.

    摘要翻译: 快速跳频收发器包括布置在第一芯片上的RF单元,第二芯片上的基带单元,布置在所述第一芯片和所述第二芯片之间的双向可操作数据和控制接口,其具有用于数据的至少一条数据线 通信,用于控制数据通信的至少一个控制线和用于提供时钟信号的至少一个时钟线;在所述RF单元内实现的存储装置,其包含特定于接收到的某个频率的所有所需的芯片设置和/或 传输数据是预期跳频序列的一部分。 收发器还包括用于在建立所述数据通信的通信链路期间的初始化阶段期间对所述存储器装置进行编程的控制装置。

    Dual carrier modulator for a multiband OFDM transceiver
    6.
    发明申请
    Dual carrier modulator for a multiband OFDM transceiver 有权
    用于多频带OFDM收发器的双载波调制器

    公开(公告)号:US20050195765A1

    公开(公告)日:2005-09-08

    申请号:US11040475

    申请日:2005-01-21

    摘要: Dual Carrier Modulator (DCM) for a Multiband OFDM (Orthogonal Frequency Division Multiplexing) Transceiver of a Ultra Wide Band (UWB) wireless personal access network transmitting OFDM modulated symbols, wherein each OFDM symbol is modulated by a predetermined number (NCBPS) of encoded bits, said Dual Carrier Modulator (1) comprising: (a) a grouping unit (1-1) for grouping NCBPS encoded bits of a serial bit stream into bit groups each having a predetermined number (m) of bits; (b) a mapping unit (1-2) for mapping each bit group received from said grouping unit to complex symbols (y) using an orthogonal transform; and (c) a reordering unit (1-3) for reordering the complex symbols (y) mapped by said mapping unit, wherein each complex symbol (y) is provided to modulate a corresponding data tone of an OFDM symbol.

    摘要翻译: 用于发射OFDM调制符号的超宽带(UWB)无线个人接入网络的多频带OFDM(正交频分复用)收发器的双载波调制器(DCM),其中每个OFDM符号由预定数量(N CBPS)调制 所述双载波调制器(1)包括:(a)用于将串行比特流的N个CBPS编码比特分组为比特组的分组单元(1 - 1) 每个具有预定数量(m)的位; (b)用于使用正交变换将从所述分组单元接收的每个位组映射到复数符号(y)的映射单元(1-2) 以及(c)用于对由所述映射单元映射的复符号(y)进行重新排序的重新排序单元(1-3),其中提供每个复数符号(y)以调制OFDM符号的相应数据音调。

    Spectrally flat delay diversity transmission
    7.
    发明授权
    Spectrally flat delay diversity transmission 失效
    光谱平坦的延迟分集传输

    公开(公告)号:US08218669B2

    公开(公告)日:2012-07-10

    申请号:US12586008

    申请日:2009-09-16

    申请人: Yossi Erlich

    发明人: Yossi Erlich

    IPC分类号: H04L1/02

    CPC分类号: H04B7/0671

    摘要: Delay diversity is implemented within a wireless system in a manner that can achieve a relatively flat spectrum in a receiving device. In at least one embodiment, phase shift values from an orthogonal P×N matrix A are used to provide phase shifts to a data packet to be transmitted from N transmit antennas, in a single spatial stream, to a remote wireless device. The matrix A is an orthogonal matrix with A·AT=P·I and P≧N. Delay diversity values are also provided to the data packet before transmission.

    摘要翻译: 延迟分集在无线系统内以可以在接收设备中实现相对平坦的频谱的方式实现。 在至少一个实施例中,使用来自正交P×N矩阵A的相移值来提供将要从单个空间流中的N个发送天线发送到远程无线设备的数据分组的相移。 矩阵A是具有A·AT = P·I和P≥N的正交矩阵。 传输之前的数据包也提供延迟分集值。

    Spectrally flat delay diversity transmission
    8.
    发明申请
    Spectrally flat delay diversity transmission 失效
    光谱平坦的延迟分集传输

    公开(公告)号:US20110064157A1

    公开(公告)日:2011-03-17

    申请号:US12586008

    申请日:2009-09-16

    申请人: Yossi Erlich

    发明人: Yossi Erlich

    IPC分类号: H04B7/02

    CPC分类号: H04B7/0671

    摘要: Delay diversity is implemented within a wireless system in a manner that can achieve a relatively flat spectrum in a receiving device. In at least one embodiment, phase shift values from an orthogonal P×N matrix A are used to provide phase shifts to a data packet to be transmitted from N transmit antennas, in a single spatial stream, to a remote wireless device. The matrix A is an orthogonal matrix with A·AT=P·I and P≧N. Delay diversity values are also provided to the data packet before transmission.

    摘要翻译: 延迟分集在无线系统内以可以在接收设备中实现相对平坦的频谱的方式实现。 在至少一个实施例中,使用来自正交P×N矩阵A的相移值来提供将要从单个空间流中的N个发射天线发送到远程无线设备的数据分组的相移。 矩阵A是具有A·AT = P·I和P≥N的正交矩阵。 传输之前的数据包也提供延迟分集值。

    Preamble generator for a multiband OFDM transceiver
    9.
    发明授权
    Preamble generator for a multiband OFDM transceiver 有权
    用于多频带OFDM收发器的前导码发生器

    公开(公告)号:US07411898B2

    公开(公告)日:2008-08-12

    申请号:US10956356

    申请日:2004-09-30

    IPC分类号: H04J11/00

    摘要: Preamble generator for a multiband frequency division multplexing (OFDM) tranceiver of a wireless personal area network (WPAN) being switchable between a time frequency interleaving (TFI)-mode wherein data packets are transmitted by said transceiver in different frequency bands according to a predetermined frequency hopping pattern and a fixed frequency interleaving (FFI) mode wherein data packets are transmitted by the transceiver in at least one fixed frequency band, wherein said preamble generator scrambles in the fixed frequency interleaving (FFI) mode a predetermined preamble of the data packets by multiplying said preamble with a pseudo random data sequence to flatten a power spectrum of said preamble.

    摘要翻译: 用于无线个域网(WPAN)的多频分频多址(OFDM)收发器的前导码发生器,可在时间频率交织(TFI)模式之间切换,其中数据分组根据预定频率在不同频带中由所述收发机发送 跳频模式和固定频率交织(FFI)模式,其中数据分组由收发机在至少一个固定频带中发送,其中所述前导码生成器以固定频率交织(FFI)模式加扰数据分组的预定前导码, 所述前同步码具有伪随机数据序列,以平坦化所述前同步码的功率谱。

    DC-offset correction circuit for a communication system and method of correcting a DC-offset in a communication system
    10.
    发明授权
    DC-offset correction circuit for a communication system and method of correcting a DC-offset in a communication system 失效
    用于通信系统的直流偏移校正电路和校正通信系统中的直流偏移的方法

    公开(公告)号:US07365662B2

    公开(公告)日:2008-04-29

    申请号:US11492575

    申请日:2006-07-25

    IPC分类号: H03M1/06

    CPC分类号: H04B1/30

    摘要: A DC-offset correction circuit includes an analog circuit to generate a plurality of analog offset-correction signal values, each of which are assigned to a hop band. The analog circuit is coupled to a tap of an analog receiver chain and includes a first analog selector to select an analog offset-correction signal value, the selected analog offset correcting signal value being assigned to a current hop band. Further, the DC-offset correction circuit includes a combiner to combine a received signal with the selected analog offset-correction signal value and feed the analog receiver chain.

    摘要翻译: DC偏移校正电路包括用于产生多个模拟偏移校正信号值的模拟电路,每个模拟偏移校正信号值被分配给跳频带。 模拟电路耦合到模拟接收器链的抽头,并且包括第一模拟选择器以选择模拟偏移校正信号值,所选择的模拟偏移校正信号值被分配给当前跳频带。 此外,DC偏移校正电路包括组合器,以将接收到的信号与所选择的模拟偏移校正信号值组合并馈送模拟接收器链。