公开(公告)号：US20250103751A1

公开(公告)日：2025-03-27

申请号：US18896914

申请日：2024-09-26

Applicant: Industrial Technology Research Institute

Inventor： Bo-Cheng Chiou ,  Chih-Sheng Lin ,  Tuo-Hung Hou ,  Chih-Ming Lai ,  Yun-Ting Ho ,  Shan-Ming Chang

IPC: G06F21/62 ,  G06F21/72 ,  H04L9/32

Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.