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    MEMORY CELL
    2.
    发明公开
    MEMORY CELL 审中-公开

    公开(公告)号：US20240079051A1

    公开(公告)日：2024-03-07

    申请号：US17983331

    申请日：2022-11-08

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Tuo-Hung Hou ,  Fu-Cheng Tsai ,  Jian-Wei Su ,  Kuo-Hua Tseng

    IPC: G11C11/412 ,  G11C11/418

    CPC classification number: G11C11/412 ,  G11C11/418

    Abstract: Disclosed is a memory cell including a first transistor having a first terminal coupled to a bit line; a second transistor having a first terminal coupled to a bit line bar; a weight storage circuit coupled between a gate terminal of the first transistor and a gate terminal of the second transistor, storing a weight value, and determining to turn on the first transistor or the second transistor according to the weight value; and a driving circuit coupled to a second terminal of the first transistor, a second terminal of the second transistor, and at least one word line, receiving at least one threshold voltage and at least one input data from the word line, and determining whether to generate an operation current on a path of the turned-on first transistor or the turned-on second transistor according to the threshold voltage and the input data.

    Computing in memory cell
    3.
    发明授权
    Computing in memory cell 有权

    公开(公告)号：US11741189B2

    公开(公告)日：2023-08-29

    申请号：US18155762

    申请日：2023-01-18

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

    IPC: G11C11/412 ,  G06F17/16

    CPC classification number: G06F17/16 ,  G11C11/412

    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, a third semiconductor element, and a fourth semiconductor element. A first terminal of the first semiconductor element receives a bias voltage. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to a first data node in the memory cell circuit. A second terminal of the third semiconductor element is adapted to receive a reference voltage. A control terminal of the third semiconductor element receives an inverted signal of the computing word-line. A first terminal of the fourth semiconductor element is coupled to a first computing bit-line. A second terminal of the fourth semiconductor element is coupled to a second computing bit-line.

    COMPUTING IN MEMORY CELL
    4.
    发明申请
    COMPUTING IN MEMORY CELL 有权

    公开(公告)号：US20210397675A1

    公开(公告)日：2021-12-23

    申请号：US17013646

    申请日：2020-09-06

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

    IPC: G06F17/16 ,  G11C11/412

    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

    Memory circuit with sense amplifier calibration mechanism
    6.
    发明授权
    Memory circuit with sense amplifier calibration mechanism 有权

    公开(公告)号：US12142342B2

    公开(公告)日：2024-11-12

    申请号：US18074528

    申请日：2022-12-05

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

    Computing in memory cell
    7.
    发明授权
    Computing in memory cell 有权

    公开(公告)号：US11599600B2

    公开(公告)日：2023-03-07

    申请号：US17013646

    申请日：2020-09-06

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Jian-Wei Su ,  Tuo-Hung Hou ,  Sih-Han Li ,  Fu-Cheng Tsai ,  Yu-Hui Lin

    IPC: G11C11/412 ,  G06F17/16

    Abstract: A computing in memory (CIM) cell includes a memory cell circuit, a first semiconductor element, a second semiconductor element, and a third semiconductor element. A first terminal of the first semiconductor element is coupled to a first computing bit-line. A control terminal of the first semiconductor element is coupled to a computing word-line. A control terminal of the second semiconductor element is coupled to the memory cell circuit. A first terminal of the second semiconductor element is coupled to a second terminal of the first semiconductor element. A first terminal of the third semiconductor element is coupled to a second terminal of the second semiconductor element. A second terminal of the third semiconductor element is coupled to a second computing bit-line. A control terminal of the third semiconductor element receives a bias voltage.

    COMPUTING CIRCUIT AND DATA COMPUTING METHOD
    9.
    发明申请
    COMPUTING CIRCUIT AND DATA COMPUTING METHOD 有权

    公开(公告)号：US20250103751A1

    公开(公告)日：2025-03-27

    申请号：US18896914

    申请日：2024-09-26

    Applicant: Industrial Technology Research Institute

    Inventor： Bo-Cheng Chiou ,  Chih-Sheng Lin ,  Tuo-Hung Hou ,  Chih-Ming Lai ,  Yun-Ting Ho ,  Shan-Ming Chang

    IPC: G06F21/62 ,  G06F21/72 ,  H04L9/32

    Abstract: A computing circuit with a de-identified architecture, a data computing method, a data processing system, and a data de-identification method are provided. The computing circuit includes an arithmetic array and a de-identification circuit. The computing circuit may perform an accumulation operation on input data to generate accumulated data by the arithmetic array. The de-identification circuit has an analog offset error determined based on an analog physical unclonable function. The computing circuit may operate the accumulated data according to the analog offset error to generate de-identification data by the de-identification circuit. It can not only provide the analog offset error through the transistors in the de-identification circuit, but also be combined with obfuscated code settings to dynamically adjusting the degree of de-identification of data.

    MEMORY CIRCUIT WITH SENSE AMPLIFIER CALIBRATION MECHANISM
    10.
    发明公开
    MEMORY CIRCUIT WITH SENSE AMPLIFIER CALIBRATION MECHANISM 审中-公开

    公开(公告)号：US20230267973A1

    公开(公告)日：2023-08-24

    申请号：US18074528

    申请日：2022-12-05

    Applicant: Industrial Technology Research Institute

    Inventor： Chih-Sheng Lin ,  Fu-Cheng Tsai ,  Tuo-Hung Hou ,  Jian-Wei Su ,  Yu-Hui Lin ,  Chih-Ming Lai

    IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10

    CPC classification number: G11C7/067 ,  G11C7/12 ,  G11C7/1063

    Abstract: According to an exemplary embodiments, the disclosure is directed to a memory circuit which includes not limited to a first half sense amplifier circuit connected to a first plurality of memory cells through a first bit line and configured to receive a unit of analog electrical signal from each of the first plurality of memory cells and to generate a first half sense amplifier output signal corresponding to the first bit line based on a first gain of the half sense amplifier and an accumulation of the units of analog signals, a locking code register circuit configured to receive a locking data and to generate a digital locking sequence, and a source selector circuit configured to receive the digital locking sequence and to generate a first adjustment signal to adjust the first half sense amplifier output signal corresponding to the first bit line by adjusting the first gain.

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