公开(公告)号：US11764166B2

公开(公告)日：2023-09-19

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute ,  Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/08 ,  H01L2224/08235

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

公开(公告)号：US11251115B1

公开(公告)日：2022-02-15

申请号：US17144144

申请日：2021-01-08

Applicant: Industrial Technology Research Institute

Inventor： Shao-An Yan ,  Chieh-Wei Feng ,  Tzu-Yang Ting ,  Tzu-Hao Yu ,  Chien-Hsun Chu ,  Jui-Wen Yang ,  Hsin-Cheng Lai

IPC: H01L23/498 ,  H01L21/48 ,  G06F30/3308 ,  G06F119/18

Abstract: A redistribution structure including a first redistribution layer is provided. The first redistribution layer includes a dielectric layer; at least one conductive structure located in the dielectric layer, wherein the at least one conductive structure has a width L; and at least one dummy structure located adjacent to the at least one conductive structure and located in the dielectric layer, and the at least one dummy structure has a width D, wherein there is a gap width S between the at least one dummy structure and the at least one conductive structure, and a degree of planarization DOP of the first redistribution layer is greater than or equal to 95%, wherein DOP=[1−(h/T)]*100%, and h refers to a difference between a highest height and a lowest height of a top surface of the dielectric layer; and T refers to a thickness of the at least one conductive structure.

公开(公告)号：US20220005768A1

公开(公告)日：2022-01-06

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/64

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.