公开(公告)号：US11387230B2

公开(公告)日：2022-07-12

申请号：US16183735

申请日：2018-11-08

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Yu-Hua Chung

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/538 ,  H01L27/12

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

公开(公告)号：US20200212033A1

公开(公告)日：2020-07-02

申请号：US16406032

申请日：2019-05-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-Hua Chung ,  Tai-Jui Wang ,  Chieh-Wei Feng

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/60

Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.

公开(公告)号：US20170170207A1

公开(公告)日：2017-06-15

申请号：US15209780

申请日：2016-07-14

Applicant: Industrial Technology Research Institute

Inventor： Tai-Jui Wang ,  Tsu-Chiang Chang ,  Yu-Hua Chung ,  Wei-Han Chen ,  Hsiao-Chiang Yao

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1218 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.

公开(公告)号：US20220005768A1

公开(公告)日：2022-01-06

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/64

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

公开(公告)号：US20190355713A1

公开(公告)日：2019-11-21

申请号：US16183735

申请日：2018-11-08

Applicant: Industrial Technology Research Institute

Inventor： Cheng-Hung Yu ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Yu-Hua Chung

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/538

Abstract: A system in package structure and an electrostatic discharge protection structure thereof are provided. The electrostatic discharge protection structure includes a redistribution layer and a first transistor array. The redistribution layer has a first electrode and a second electrode. The first transistor array is coupled to a pin end of at least one integrated circuit, the first electrode and the second electrode. The first transistor array has a plurality of transistors. A plurality of first transistors of the transistors are coupled in parallel, and a plurality of second transistors of the transistors are coupled in parallel. The first transistors and the second transistors are configured to be turned on for dissipating an electrostatic discharge current.

公开(公告)号：US11764166B2

公开(公告)日：2023-09-19

申请号：US17216686

申请日：2021-03-30

Applicant: Industrial Technology Research Institute ,  Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Wen Yang ,  Hsin-Cheng Lai ,  Chieh-Wei Feng ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Tzu-Yang Ting

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/08 ,  H01L2224/08235

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

公开(公告)号：US10083989B2

公开(公告)日：2018-09-25

申请号：US15209780

申请日：2016-07-14

Applicant: Industrial Technology Research Institute

Inventor： Tai-Jui Wang ,  Tsu-Chiang Chang ,  Yu-Hua Chung ,  Wei-Han Chen ,  Hsiao-Chiang Yao

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1218 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device is provided to include a flexible substrate, a barrier layer, a heat insulating layer, a device layer, a dielectric material later and a stress absorbing layer. The barrier layer is disposed on the flexible substrate. The heat insulating layer is disposed on the barrier layer, wherein the heat insulating layer has a thermal conductivity of less than 20 W/mK. The device layer is disposed on the heat insulating layer. The dielectric material layer is disposed on the device layer, and the dielectric material layer and the heat insulating layer include at least one trench. The stress absorbing layer is disposed on the dielectric material layer, and the stress absorbing layer fills into the at least one trench.

公开(公告)号：US20230165529A1

公开(公告)日：2023-06-01

申请号：US17584394

申请日：2022-01-26

Applicant: Industrial Technology Research Institute

Inventor： Yu-Hua Chung ,  Tai-Jui Wang ,  Chieh-Wei Feng ,  Tzu-Yang Ting ,  Jui-Wen Yang

IPC: A61B5/00 ,  A61B5/263 ,  A61B5/277 ,  A61B5/271

CPC classification number: A61B5/683 ,  A61B5/7203 ,  A61B5/263 ,  A61B5/277 ,  A61B5/271 ,  A61B2562/046

Abstract: A physiological sensing device is provided, including an electronic component, a coupled sensing electrode, a coupling dielectric layer, and a wire layer. The coupled sensing electrode is configured to sense a physiological signal of an object, wherein there is a capacitance value between the object and the coupled sensing electrode. The coupling dielectric layer is disposed under the coupled sensing electrode, so that the capacitance value is between 1 nF and 10 nF. The wire layer is electrically connected to the electronic component and the coupled sensing electrode.

公开(公告)号：US11088135B2

公开(公告)日：2021-08-10

申请号：US16406032

申请日：2019-05-08

Applicant: Industrial Technology Research Institute

Inventor： Yu-Hua Chung ,  Tai-Jui Wang ,  Chieh-Wei Feng

IPC: H01L27/02 ,  H01L23/60 ,  H01L23/522

Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.

公开(公告)号：US10941498B2

公开(公告)日：2021-03-09

申请号：US16447358

申请日：2019-06-20

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chien-Hsun Chu ,  Chien-Chou Tseng ,  Ming-Huan Yang ,  Tai-Jui Wang ,  Yu-Hua Chung ,  Chieh-Wei Feng

IPC: H01L29/40 ,  C25D5/02 ,  C25D7/12 ,  H01L23/528 ,  H01L21/288

Abstract: A panel to be plated is provided. The panel includes a substrate and an electric field compensation structure. The substrate includes a plurality of units to be plated each including a first pattern to be plated. The electric field compensation structure is disposed on the substrate. The electric field compensation structure includes a second pattern to be plated surrounding at least one of the units to be plated. A ratio of an area of the first pattern to be plated of the units to be plated to an area of the second pattern to be plated of the electric field compensation structure is in a range from 1:0.07 to 1:0.3.