公开(公告)号：US20230144030A1

公开(公告)日：2023-05-11

申请号：US17546074

申请日：2021-12-09

Applicant: Industrial Technology Research Institute

Inventor： Chih-Wei Liu ,  Yu-Chuan Li

IPC: G06F7/50 ,  G06F7/523 ,  G06F7/483

CPC classification number: G06F7/50 ,  G06F7/523 ,  G06F7/483

Abstract: A multi-input multi-output adder and an operating method thereof are proposed. The multi-input multi-output adder includes an adder circuitry configured to perform an operation. The operation includes the following. A first source operand and a second source operand are added to generate a first summed operand. Direct truncation is performed on at least one last bit of the first summed operand to generate a first truncated-summed operand. Right shift is performed on the first truncated-summed operand to generate a first shifted-summed operand. A bit number of the right shift of the first truncated-summed operand is equal to a bit number of the direct truncation of the first summed operand.