公开(公告)号：US11239830B2

公开(公告)日：2022-02-01

申请号：US17198477

申请日：2021-03-11

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Anton Huber

IPC: H03K3/037 ,  H03K3/012 ,  H03K3/3562 ,  H03K3/356

Abstract: A master-slave D flip-flop is disclosed having gates configured to supply two second intermediate signals as a function of first intermediate signals and a clock signal, and a slave circuit connected to a transfer circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured, when the second intermediate signals have, after a preceding pair of states, a predetermined pair of states, to maintain the at least one output signal as given by the preceding pair of states. The transfer circuit has a control input and is configured to generate the second intermediate signals to have the predetermined pair of states in response to a predetermined control signal state at the control input.

公开(公告)号：US20210288633A1

公开(公告)日：2021-09-16

申请号：US17198477

申请日：2021-03-11

Applicant: Infineon Technologies AG

Inventor： Thomas Kuenemund ,  Anton Huber

IPC: H03K3/037

Abstract: A master-slave D flip-flop is disclosed having gates configured to supply two second intermediate signals as a function of first intermediate signals and a clock signal, and a slave circuit connected to a transfer circuit to form at least one output signal of the flip-flop from the second intermediate signals. The slave circuit is configured, when the second intermediate signals have, after a preceding pair of states, a predetermined pair of states, to maintain the at least one output signal as given by the preceding pair of states. The transfer circuit has a control input and is configured to generate the second intermediate signals to have the predetermined pair of states in response to a predetermined control signal state at the control input.