公开(公告)号：US20210248013A1

公开(公告)日：2021-08-12

申请号：US17167546

申请日：2021-02-04

Applicant: Infineon Technologies AG

Inventor： Konrad Walluszik ,  Juergen Schaefer

IPC: G06F9/50 ,  G06F9/54

Abstract: A data processing device is provided. The data processing device includes at least one processor circuit, at least one additional circuit, an accelerator circuit, a first data connection which at least connects the at least one processor circuit to the accelerator circuit and is configured to exchange data between the at least one processor circuit and the accelerator circuit, a second data connection which connects the at least one processor circuit to the at least one additional circuit and is configured to exchange data between the at least one additional circuit and the processor circuit, wherein the first data connection has a higher data rate or a lower latency than the second data connection, and includes an address segment having a first address range, which has at least one first address each for the at least one additional circuit and the accelerator circuit, and a second address range which has at least one second address each for the at least one additional circuit and the accelerator circuit, wherein the data processing device is configured to exchange data using the first data connection when addressing using one of the first addresses, and to exchange data using the second data connection when addressing using one of the second addresses.

公开(公告)号：US11416301B2

公开(公告)日：2022-08-16

申请号：US17167546

申请日：2021-02-04

Applicant: Infineon Technologies AG

Inventor： Konrad Walluszik ,  Juergen Schaefer

IPC: G06F9/50 ,  G06F9/54

Abstract: A data processing device is provided. The data processing device includes at least one processor circuit, at least one additional circuit, an accelerator circuit, a first data connection which at least connects the at least one processor circuit to the accelerator circuit and is configured to exchange data between the at least one processor circuit and the accelerator circuit, a second data connection which connects the at least one processor circuit to the at least one additional circuit and is configured to exchange data between the at least one additional circuit and the processor circuit, wherein the first data connection has a higher data rate or a lower latency than the second data connection, and includes an address segment having a first address range, which has at least one first address each for the at least one additional circuit and the accelerator circuit, and a second address range which has at least one second address each for the at least one additional circuit and the accelerator circuit, wherein the data processing device is configured to exchange data using the first data connection when addressing using one of the first addresses, and to exchange data using the second data connection when addressing using one of the second addresses.

公开(公告)号：US20230128057A1

公开(公告)日：2023-04-27

申请号：US17965166

申请日：2022-10-13

Applicant: Infineon Technologies AG

Inventor： Muhammad Hassan ,  Konrad Walluszik ,  Juergen Schaefer

IPC: G06N3/063 ,  G06F7/544

Abstract: A system for executing an artificial neural network having a plurality of interconnected nodes, the system includes a memory storing weight values of the neural network. The memory can be configured to a store node value and a mask bit value for each of the plurality of nodes of the neural network. Further the system can include multiply and accumulate (MAC) units to perform operations for determining node values. The system includes a control unit circuitry that, during execution of the neural network, dynamically controls operations of the MAC units to cause a reduction in a number of calculations to be performed by the MAC units. The control unit circuitry causes the MAC units to perform operations involving a subset of the plurality of nodes to avoid performing operations involving nodes of the plurality nodes that are outside of the subset.