公开(公告)号：US20210096899A1

公开(公告)日：2021-04-01

申请号：US16585507

申请日：2019-09-27

Applicant: Infineon Technologies AG

Inventor： Manoj Kumar Harihar ,  Romain Ygnace

IPC: G06F9/455 ,  G06F12/0875

Abstract: A cache circuit associated with a hypervisor system is disclosed. The cache circuit comprises a cache memory circuit comprising a plurality of cachelines, wherein each cacheline is configured to store data associated with one or more virtual machines (VMs) of a plurality of VMs associated with the hypervisor system and a plurality of tag array entries respectively associated with the plurality of cachelines. In some embodiments, each tag array entry of the plurality of tag entries comprises a tag field configured to store a tag identifier (ID) that identifies an address of a main memory circuit to which a data stored in the corresponding cacheline is associated and a VM tag field configured to store a VM ID associated with a VM to which the data stored in the corresponding cacheline is associated.

公开(公告)号：US20250094209A1

公开(公告)日：2025-03-20

申请号：US18959787

申请日：2024-11-26

Applicant: Infineon Technologies AG

Inventor： Manoj Kumar Harihar ,  Arndt Voigtlaender

IPC: G06F9/46 ,  G06F9/30 ,  G06F9/448

Abstract: Systems, devices, circuitries, and methods are disclosed for identifying, within a call instruction, context registers for storing prior to a jump to another subroutine. In one example, a method includes receiving, while executing a first subroutine, a call instruction that includes a first opcode and a first set of bits, wherein the call instruction identifies a first target address, wherein the first target address stores a first instruction of a set of instructions for performing a second subroutine. A first set of context registers mapped to the first set of bits is identified and content of the first set of context registers is stored in first memory allocated for context storage for the first subroutine. The first instruction stored in the first target address is executed.

公开(公告)号：US12182572B2

公开(公告)日：2024-12-31

申请号：US17401718

申请日：2021-08-13

Applicant: Infineon Technologies AG

Inventor： Manoj Kumar Harihar ,  Arndt Voigtlaender

IPC: G06F9/30 ,  G06F9/448 ,  G06F9/46

Abstract: Systems, devices, circuitries, and methods are disclosed for identifying, within a call instruction, context registers for storing prior to a jump to another subroutine. In one example, a method includes receiving, while executing a first subroutine, a call instruction that includes a first opcode and identifies a first target address, wherein the first target address stores instructions for performing a second subroutine. A first set of context registers identified by the call instruction is determined and the content of the first set of context registers is stored in first memory allocated for context storage for the first subroutine prior to executing the instruction stored in the first target address.

公开(公告)号：US20230051855A1

公开(公告)日：2023-02-16

申请号：US17401718

申请日：2021-08-13

Applicant: Infineon Technologies AG

Inventor： Manoj Kumar Harihar ,  Arndt Voigtlaender

IPC: G06F9/46 ,  G06F9/38 ,  G06F9/50

Abstract: Systems, devices, circuitries, and methods are disclosed for identifying, within a call instruction, context registers for storing prior to a jump to another subroutine. In one example, a method includes receiving, while executing a first subroutine, a call instruction that includes a first opcode and identifies a first target address, wherein the first target address stores instructions for performing a second subroutine. A first set of context registers identified by the call instruction is determined and the content of the first set of context registers is stored in first memory allocated for context storage for the first subroutine prior to executing the instruction stored in the first target address.

公开(公告)号：US11232034B2

公开(公告)日：2022-01-25

申请号：US16585507

申请日：2019-09-27

Applicant: Infineon Technologies AG

Inventor： Manoj Kumar Harihar ,  Romain Ygnace

IPC: G06F12/0846 ,  G06F9/455 ,  G06F12/0875

Abstract: A cache circuit associated with a hypervisor system is disclosed. The cache circuit comprises a cache memory circuit comprising a plurality of cachelines, wherein each cacheline is configured to store data associated with one or more virtual machines (VMs) of a plurality of VMs associated with the hypervisor system and a plurality of tag array entries respectively associated with the plurality of cachelines. In some embodiments, each tag array entry of the plurality of tag entries comprises a tag field configured to store a tag identifier (ID) that identifies an address of a main memory circuit to which a data stored in the corresponding cacheline is associated and a VM tag field configured to store a VM ID associated with a VM to which the data stored in the corresponding cacheline is associated.