公开(公告)号：US20220199481A1

公开(公告)日：2022-06-23

申请号：US17542905

申请日：2021-12-06

Applicant: Infineon Technologies AG

Inventor： Raphael HELLWIG ,  Philip AMOS ,  Walter HARTNER

IPC: H01L23/34 ,  H01L23/498 ,  H01L23/552

Abstract: A circuit arrangement has a chip arrangement in the form of an embedded Wafer Level Ball Grid Array (eWLB) arrangement with solder contacts on one side and a thermal interface on a side of the chip arrangement facing away from the solder contacts which is designed to dissipate heat from the semiconductor chip. In examples, the thermal interface has a thermally and electrically conductive material, wherein in a top view of the chip arrangement, a contact area in which the thermally and electrically conductive material is in thermal contact with the chip arrangement is limited to the fan-out area. In examples, the thermal interface has at least one RF absorption layer which is designed to absorb electromagnetic radiation at an operating frequency of the semiconductor chip.