公开(公告)号：US20210373145A1

公开(公告)日：2021-12-02

申请号：US17397271

申请日：2021-08-09

Applicant: Infineon Technologies AG

Inventor： Niels CHRISTOFFERS ,  Sanaz HADIPOUR ABKENAR ,  Soumya KRISHNAPURAM SIREESH ,  Christoph WAGNER

IPC: G01S13/34 ,  H03M1/06 ,  G01S13/32 ,  G01S13/36

Abstract: Radar frequency range signals (e.g., 1 to 100 gigahertz) are often generated by upconverting a reference frequency to a transmission frequency, and a received signal may be downconverted to analyze information encoded on the transmission via modulation. Modulation may be achieved via a fractional frequency divider in a phase-locked loop, but fractional spurs may reduce the signal-to-noise ratio. Additionally, the ramp slope may vary due to phase-locked loop momentum. Instead, a clock generator may generate clock signals for a digital front end comprising a digital signal modulator that generates modulated digital values comprising quadrature representations of a radar modulation signal, which are encoded by a radiofrequency digital-to-analog converter (RF-DAC). The RF-DAC analog signal may be upconverted to a radar frequency and transmitted. A receiver may receive, downconvert, and analyze a reflection of the radar transmission, e.g., to perform range detection based on a frequency ramp encoded by the radar transmission.