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公开(公告)号：US20180374941A1
公开(公告)日：2018-12-27
申请号：US15628723
申请日：2017-06-21
发明人： Seong-Eun Park , Jianwei Wan , Mihir Tungare , Peter Kim , Srinivasan Kannan
IPC分类号： H01L29/778 , H01L29/267 , H01L21/02
摘要： A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
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公开(公告)号：US20200303531A1
公开(公告)日：2020-09-24
申请号：US16895585
申请日：2020-06-08
发明人： Seong-Eun Park , Jianwei Wan , Mihir Tungare , Peter Kim , Srinivasan Kannan
IPC分类号： H01L29/778 , H01L21/02 , H01L29/267
摘要： A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
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公开(公告)号：US20220344499A1
公开(公告)日：2022-10-27
申请号：US17861913
申请日：2022-07-11
发明人： Seong-Eun Park , Jianwei Wan , Mihir Tungare , Peter Kim , Srinivasan Kannan
IPC分类号： H01L29/778 , H01L21/02 , H01L29/267
摘要： A method includes providing a type IV semiconductor substrate having a main surface, forming a type III-V semiconductor channel region over the type IV semiconductor substrate, the type III-V semiconductor channel region comprising a two-dimensional carrier gas, forming a type III-V semiconductor lattice transition region between the type IV semiconductor substrate and the type III-V semiconductor channel region, wherein forming the type III-V semiconductor lattice transition region incudes forming a first lattice transition layer over the type IV semiconductor substrate, the first lattice transition layer having a first metallic concentration, forming a third lattice transition layer over the first lattice transition layer, the third lattice transition layer having a third metallic concentration higher than the first metallic concentration, and forming a fourth lattice transition layer over the third lattice transition layer, the fourth lattice transition layer having a fourth metallic lower than the first metallic concentration.
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公开(公告)号：US10720520B2
公开(公告)日：2020-07-21
申请号：US15628723
申请日：2017-06-21
发明人： Seong-Eun Park , Jianwei Wan , Mihir Tungare , Peter Kim , Srinivasan Kannan
IPC分类号： H01L27/14 , H01L29/778 , H01L21/02 , H01L29/267 , H01L29/20
摘要： A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
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公开(公告)号：US11387355B2
公开(公告)日：2022-07-12
申请号：US16895585
申请日：2020-06-08
发明人： Seong-Eun Park , Jianwei Wan , Mihir Tungare , Peter Kim , Srinivasan Kannan
IPC分类号： H01L29/20 , H01L29/205 , H01L29/778 , H01L21/02 , H01L29/267
摘要： A type IV semiconductor substrate having a main surface is provided. A type III-V semiconductor channel region that includes a two-dimensional carrier gas is formed over the type IV semiconductor substrate. A type III-V semiconductor lattice transition region that is configured to alleviate mechanical stress arising from lattice mismatch is formed between the type IV semiconductor substrate and the type III-V semiconductor channel region. Forming the type III-V semiconductor lattice transition region includes forming a first lattice transition layer having a first metallic concentration over the type IV semiconductor substrate, forming a third lattice transition layer having a third metallic concentration that is higher than the first metallic concentration over the first lattice transition layer, and forming a fourth lattice transition layer having a fourth metallic concentration that is lower than the first metallic concentration over the third lattice transition layer.
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