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公开(公告)号：US11316043B2
公开(公告)日：2022-04-26
申请号：US16717445
申请日：2019-12-17
发明人： Robert Paul Haase , Jyotshna Bhandari , Heimo Hofer , Ling Ma , Ashita Mirchandani , Harsh Naik , Martin Poelzl , Martin Henning Vielemeyer , Britta Wutte
IPC分类号： H01L29/78 , H01L29/423 , H01L29/45 , H01L29/66
摘要： A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.
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公开(公告)号：US12119400B2
公开(公告)日：2024-10-15
申请号：US17714660
申请日：2022-04-06
发明人： Robert Paul Haase , Jyotshna Bhandari , Heimo Hofer , Ling Ma , Ashita Mirchandani , Harsh Naik , Martin Poelzl , Martin Henning Vielemeyer , Britta Wutte
IPC分类号： H01L29/78 , H01L29/423 , H01L29/45 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/456 , H01L29/66734
摘要： A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.
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公开(公告)号：US20220231163A1
公开(公告)日：2022-07-21
申请号：US17714660
申请日：2022-04-06
发明人： Robert Paul Haase , Jyotshna Bhandari , Heimo Hofer , Ling Ma , Ashita Mirchandani , Harsh Naik , Martin Poelzl , Martin Henning Vielemeyer , Britta Wutte
IPC分类号： H01L29/78 , H01L29/423 , H01L29/45 , H01L29/66
摘要： A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.
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