公开(公告)号：US12080789B2

公开(公告)日：2024-09-03

申请号：US17481446

申请日：2021-09-22

Applicant: Infineon Technologies Austria AG

Inventor： Oliver Blank ,  Heimo Hofer ,  Andreas Kleinbichler ,  Martin Poelzl

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/3065 ,  H01L29/49 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7811 ,  H01L21/28123 ,  H01L21/3065 ,  H01L29/4925 ,  H01L29/66712 ,  H01L29/7813 ,  H01L29/0865 ,  H01L29/41766

Abstract: A semiconductor die is described. The semiconductor die includes a semiconductor body having an active region, a metallization formed on the semiconductor body, and a passivation formed on the metallization. The metallization includes at least one of a titanium layer, a titanium nitride layer, and a tungsten layer. The passivation includes a silicon oxide layer. Corresponding methods of manufacturing and using the semiconductor die are also described.

公开(公告)号：US20240194754A1

公开(公告)日：2024-06-13

申请号：US18443354

申请日：2024-02-16

Applicant: Infineon Technologies Austria AG

Inventor： Weichun Huang ,  Martin Poelzl ,  Thomas Martin Feil ,  Maximilian Roesch

IPC: H01L29/423 ,  H01L21/768 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/423 ,  H01L21/76805 ,  H01L21/76831 ,  H01L27/0629 ,  H01L29/0634 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7843 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/872

Abstract: A semiconductor device includes a contact opening extending through a source region and at least into a body region formed in a semiconductor substrate. The contact opening forms at least one sidewall in the semiconductor substrate. An electrically insulative spacer partially covers the at least one sidewall. A contact plug is in the contact opening. A body contact region is formed in the semiconductor substrate adjacent a bottom of the contact opening.

公开(公告)号：US20200303498A1

公开(公告)日：2020-09-24

申请号：US16896593

申请日：2020-06-09

Applicant: Infineon Technologies Austria AG

Inventor： Martin Poelzl ,  Robert Haase ,  Maximilian Roesch ,  Sylvain Leomant ,  Andreas Meiser ,  Bernhard Goller ,  Ravi Keshav Joshi

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/225 ,  H01L27/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device includes: forming one or more device epitaxial layers over a main surface of a doped Si base substrate; forming a diffusion barrier structure including alternating layers of Si and oxygen-doped Si in an upper part of the doped Si base substrate adjacent the main surface of the doped Si base substrate, in a lower part of the one or more device epitaxial layers adjacent the main surface of the doped Si base substrate, or in one or more additional epitaxial layers disposed between the main surface of the doped Si base substrate and the one or more device epitaxial layers; and forming a gate above the diffusion barrier structure.

公开(公告)号：US10580888B1

公开(公告)日：2020-03-03

申请号：US16058631

申请日：2018-08-08

Applicant: Infineon Technologies Austria AG

Inventor： Oliver Blank ,  Thomas Feil ,  Maximilian Roesch ,  Martin Poelzl ,  Robert Haase ,  Sylvain Leomant ,  Bernhard Goller ,  Andreas Meiser

IPC: H01L29/78 ,  H01L21/76 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3063

Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.

公开(公告)号：US10249723B2

公开(公告)日：2019-04-02

申请号：US15854236

申请日：2017-12-26

Applicant: Infineon Technologies Austria AG

Inventor： Heimo Hofer ,  Martin Poelzl ,  Maximilian Roesch ,  Britta Wutte

IPC: H01L21/763 ,  H01L29/417 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/739

Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.

公开(公告)号：US20190035915A1

公开(公告)日：2019-01-31

申请号：US16045335

申请日：2018-07-25

Applicant: Infineon Technologies Austria AG

Inventor： Ralf Siemieniec ,  Robert Haase ,  Gerhard Noebauer ,  Martin Poelzl

IPC: H01L29/66 ,  H01L29/78

Abstract: Disclosed is a transistor device. The transistor device includes: in a semiconductor body, a drift region, a body region adjoining the drift region, and a source region separated from the drift region by the body region; a gate electrode dielectrically insulated from the body region by a gate dielectric; a source electrode electrically connected to the source region; at least one field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a rectifier element coupled between the source electrode and the field electrode. The field electrode and the field electrode dielectric are arranged in a first trench that extends from a first surface of the semiconductor body into the semiconductor body. The rectifier element is integrated in the first trench in a rectifier region that is adjacent at least one of the source region and the body region.

公开(公告)号：US20170110331A1

公开(公告)日：2017-04-20

申请号：US15293533

申请日：2016-10-14

Applicant: Infineon Technologies Austria AG

Inventor： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Georg Ehrentraut ,  Petra Fischer ,  Richard Gaisberger ,  Christoph Gruber ,  Martin Poelzl ,  Juergen Steinbrenner

IPC: H01L21/308 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/3063 ,  H01L29/739

CPC classification number: H01L21/3088 ,  H01L21/3063 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7813

Abstract: A method for forming a semiconductor device includes etching, in a masked etching process, through a layer stack located on a surface of a semiconductor substrate to expose the semiconductor substrate at unmasked regions of the layer stack. The method further includes etching, in a selective etching process, at least a first layer of the layer stack located adjacently to the semiconductor substrate. A second layer of the layer stack is less etched or non-etched compared to the selective etching of the first layer of the layer stack, such that the first layer of the layer stack is laterally etched back between the semiconductor substrate and the second layer of the layer stack. The method further includes growing semiconductor material on regions of the surface of the semiconductor substrate exposed after the selective etching process.

公开(公告)号：US09620636B2

公开(公告)日：2017-04-11

申请号：US14829526

申请日：2015-08-18

Applicant: Infineon Technologies Austria AG

Inventor： Ralf Siemieniec ,  Oliver Blank ,  Franz Hirler ,  Michael Hutzler ,  Martin Poelzl

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes field electrode structures regularly arranged in lines in a cell area and forming a first portion of a regular pattern. Termination structures are formed in an inner edge area surrounding the cell area, wherein at least portions of the termination structures form a second portion of the regular pattern. Cell mesas separate neighboring ones of the field electrode structures from each other in the cell area and include first portions of a drift zone, wherein a voltage applied to a gate electrode controls a current flow through the cell mesas. At least one doped region forms a homojunction with the drift zone in the inner edge area.

公开(公告)号：US20170011927A1

公开(公告)日：2017-01-12

申请号：US15273589

申请日：2016-09-22

Applicant: Infineon Technologies Austria AG

Inventor： Juergen Steinbrenner ,  Markus Kahn ,  Helmut Schoenherr ,  Ravi Joshi ,  Heimo Hofer ,  Martin Poelzl ,  Harald Huetter

IPC: H01L21/28 ,  H01L29/06 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L21/28185 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/76801 ,  H01L21/76828 ,  H01L23/5329 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.

Abstract translation: 沉积绝缘层的方法包括通过以第一流速使用硅源和以第二流量的掺杂剂源沉积硅酸盐玻璃层来在特征的侧壁上进行初次沉积。 掺杂剂源的流量与硅源的流量的比率是第一比率。 该方法还包括通过增加硅源相对于掺杂源的流动的流动来在特征的侧壁上进行二次沉积。 掺杂剂源的流量与硅源的流量的比率是低于第一比率的第二比例，并且在执行二次沉积之后停止硅源的流动。 停止流动后进行回流处理。 在回流处理之后，特征的侧壁上的硅酸盐玻璃层的厚度变化在1％至20％之间。

公开(公告)号：US09461004B2

公开(公告)日：2016-10-04

申请号：US14725794

申请日：2015-05-29

Applicant: Infineon Technologies Austria AG

Inventor： Andreas Meiser ,  Markus Zundel ,  Martin Poelzl ,  Paul Ganitzer ,  Georg Ehrentraut

IPC: H01L21/78 ,  H01L23/00 ,  H01L21/762 ,  H01L23/544 ,  H01L21/822 ,  H01L23/538 ,  H01L21/784 ,  H01L29/78

CPC classification number: H01L23/544 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/78 ,  H01L21/784 ,  H01L21/822 ,  H01L23/5384 ,  H01L23/562 ,  H01L29/78 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor workpiece includes a semiconductor substrate, at least two chip areas, components of semiconductor devices being formed in the semiconductor substrate in the at least two chip areas, and a separation trench disposed between adjacent chip areas. The separation trench is formed in a first main surface of the semiconductor substrate and extends from the first main surface to a second main surface of the semiconductor substrate. The second main surface is disposed opposite to the first main surface. The separation trench is filled with at least one sacrificial material.

Abstract translation: 半导体工件包括半导体衬底，至少两个芯片区域，在至少两个芯片区域中的半导体衬底中形成半导体器件的部件，以及设置在相邻芯片区域之间的分离沟槽。 分离沟槽形成在半导体衬底的第一主表面中，并从半导体衬底的第一主表面延伸到第二主表面。 第二主表面与第一主表面相对设置。 分离槽填充有至少一种牺牲材料。