公开(公告)号：US08433881B2

公开(公告)日：2013-04-30

申请号：US13357339

申请日：2012-01-24

申请人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

发明人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

IPC分类号： G06F9/355

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。

公开(公告)号：US09184953B2

公开(公告)日：2015-11-10

申请号：US11721050

申请日：2005-12-13

申请人： Ingolf Held ,  Marcus M. G. Quax ,  Paulus W. F. Gruijters

发明人： Ingolf Held ,  Marcus M. G. Quax ,  Paulus W. F. Gruijters

IPC分类号： G06F9/30 ,  H04L27/38 ,  H04L25/06

CPC分类号： H04L25/067 ,  G06F9/30007 ,  H04L27/38

摘要： A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.

摘要翻译： 可编程信号处理电路具有指令处理电路（23,24.26），其具有包括解映射指令的指令集。 指令处理电路（23,24,26）具有操作数输入（30a），用于接收来自寄存器文件（22）的解映射指令的复数操作数和用于写入解映射的解映射结果的结果输出（34） 指令寄存器文件（22）。 指令处理电路（23,24,26）响应于解映射指令来确定至少四个比特量度，每个指标在复平面中指示复数相对于相应边界线的相对位置。 指令处理电路（23,24,26）在解映射结果中将至少四位比特度量的组合写入结果输出（34）。

公开(公告)号：US08108651B2

公开(公告)日：2012-01-31

申请号：US11721052

申请日：2005-12-13

申请人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

发明人： Paulus W. F. Gruijters ,  Marcus M. G. Quax ,  Ingolf Held

IPC分类号： G06F12/06 ,  H04N7/12

CPC分类号： G06F9/30032 ,  G06F9/30029 ,  G06F9/30043 ,  G06F9/345 ,  G06F9/3455

摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.

摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。

公开(公告)号：US07853860B2

公开(公告)日：2010-12-14

申请号：US11721053

申请日：2005-12-13

申请人： Paulus W. F. Gruijters ,  Marcus M. G. Quax

发明人： Paulus W. F. Gruijters ,  Marcus M. G. Quax

IPC分类号： H03M13/03

CPC分类号： H04L1/0069 ,  G06F9/30018 ,  G06F9/30145 ,  H03M13/6362

摘要： A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result. The instruction processing circuit (23, 24, 26) changes the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.

摘要翻译： 可编程信号处理电路具有指令处理电路（23,24,26），其中指令集包括解读指令。 指令处理电路（23,24,26）通过从比特度量操作数复制比特度量并且在解穿孔结果中从比特度量操作数的比特度量之间插入一个或多个预定比特度量值来形成解穿孔结果。 指令处理电路（23,24,26）相对于比特度量操作数中的复制比特度量相对于彼此的相对位置，在折叠结果中相对于彼此改变复制比特度量的相对位置 在一定程度上适应插入的预定位度量值或值。