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公开(公告)号：US08433881B2
公开(公告)日：2013-04-30
申请号：US13357339
申请日：2012-01-24
IPC分类号： G06F9/355
CPC分类号： G06F9/30032 , G06F9/30029 , G06F9/30043 , G06F9/345 , G06F9/3455
摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.
摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。
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2.发明授权Programmable signal processing circuit and method of demodulating via a demapping instruction 有权可编程信号处理电路和解映射指令的解调方法公开(公告)号：US09184953B2
公开(公告)日：2015-11-10
申请号：US11721050
申请日：2005-12-13
CPC分类号： H04L25/067 , G06F9/30007 , H04L27/38
摘要： A programmable signal processing circuit has an instruction processing circuit (23, 24. 26), which has an instruction set that comprises a demapping instruction. The instruction processing circuit (23, 24, 26) has an operand input (30a) for receiving a complex number operand of the demapping instruction from a register file (22) and a result output (34) for writing a demapping result of the demapping instruction to the register file (22). The instruction processing circuit (23, 24, 26) determines at least four bit metrics in response to the demapping instruction, each indicating a relative position of the complex number relative to respective border line in a complex plane. The instruction processing circuit (23, 24, 26) writes a combination of the at least four bit metrics together to the result output (34) in the demapping result.
摘要翻译： 可编程信号处理电路具有指令处理电路（23,24.26），其具有包括解映射指令的指令集。 指令处理电路（23,24,26）具有操作数输入（30a），用于接收来自寄存器文件（22）的解映射指令的复数操作数和用于写入解映射的解映射结果的结果输出（34） 指令寄存器文件（22）。 指令处理电路（23,24,26）响应于解映射指令来确定至少四个比特量度，每个指标在复平面中指示复数相对于相应边界线的相对位置。 指令处理电路（23,24,26）在解映射结果中将至少四位比特度量的组合写入结果输出（34）。
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公开(公告)号：US08108651B2
公开(公告)日：2012-01-31
申请号：US11721052
申请日：2005-12-13
CPC分类号： G06F9/30032 , G06F9/30029 , G06F9/30043 , G06F9/345 , G06F9/3455
摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.
摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。
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公开(公告)号：US07853860B2
公开(公告)日：2010-12-14
申请号：US11721053
申请日：2005-12-13
IPC分类号： H03M13/03
CPC分类号： H04L1/0069 , G06F9/30018 , G06F9/30145 , H03M13/6362
摘要： A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23, 24, 26) forms the depuncture result by copying bit metrics from a bit metrics operand and inserting one or more predetermined bit metric values between the bit metrics from the bit metric operand in the depuncture result. The instruction processing circuit (23, 24, 26) changes the relative locations of the copied bit metrics with respect to each other in the depuncture result as compared to the relative locations of the copied bit metrics with respect to each other in the bit metric operand, to an extent needed for accommodating the inserted predetermined bit metric value or values.
摘要翻译： 可编程信号处理电路具有指令处理电路（23,24,26），其中指令集包括解读指令。 指令处理电路（23,24,26）通过从比特度量操作数复制比特度量并且在解穿孔结果中从比特度量操作数的比特度量之间插入一个或多个预定比特度量值来形成解穿孔结果。 指令处理电路（23,24,26）相对于比特度量操作数中的复制比特度量相对于彼此的相对位置，在折叠结果中相对于彼此改变复制比特度量的相对位置 在一定程度上适应插入的预定位度量值或值。
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公开(公告)号：US20120120310A1
公开(公告)日：2012-05-17
申请号：US13357339
申请日：2012-01-24
IPC分类号： H04N7/01
CPC分类号： G06F9/30032 , G06F9/30029 , G06F9/30043 , G06F9/345 , G06F9/3455
摘要： A programmable signal processing circuit is used to (de-)interleave a data stream. Data from the signal stream is stored in a data memory (28) and read in a different sequence. The programmable signal processing circuit is used for computing addresses, for use in said storing and/or reading. The programmable signal processing circuit has an instruction set that contains an instruction to compute the addresses from preceding addresses that have been used for said storing and/or reading. In response to the instruction the programmable signal processing circuit permutes positions of a plurality of bits from the old address operand and forms of a bit of the new address result as a logic function of a combination of bits from the old address operand. Successive addresses are formed by means of repeated execution of a program loop that contains an address update instruction for computing the addresses.
摘要翻译： 可编程信号处理电路用于（去）交织数据流。 来自信号流的数据被存储在数据存储器（28）中，并以不同的顺序读取。 可编程信号处理电路用于计算用于所述存储和/或读取的地址。 可编程信号处理电路具有指令集，其包含用于计算已经用于所述存储和/或读取的先前地址的地址的指令。 响应于指令，可编程信号处理电路将来自旧地址操作数的多个位的位置和新地址结果的位的形式作为来自旧地址操作数的位组合的逻辑功能。 通过重复执行包含用于计算地址的地址更新指令的程序循环来形成连续地址。
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6.发明授权Method and apparatus for optimizing conversion of input data to output data 失效用于优化输入数据到输出数据的转换的方法和装置公开(公告)号：US06438568B1
公开(公告)日：2002-08-20
申请号：US09287162
申请日：1999-04-06
IPC分类号： G06F1714
CPC分类号： G06F17/14
摘要： The device for converting series of input data elements to series of output data elements is provided with a memory (110) for containing the series of input and output data elements. This memory (110) is embodied so as to successively read a series of input data elements and write a series of output data elements during a single clock cycle.
摘要翻译： 用于将一系列输入数据元素转换为一系列输出数据元素的装置设置有用于容纳一系列输入和输出数据元素的存储器（110）。 该存储器（110）被实现为在单个时钟周期期间连续读取一系列输入数据元素并写入一系列输出数据元素。
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7.发明授权Electronic stream processing circuit with locally controlled parameter updates, and method of designing such a circuit 失效具有局部控制参数更新的电子流处理电路，以及设计这种电路的方法公开(公告)号：US07900171B2
公开(公告)日：2011-03-01
申请号：US12256334
申请日：2008-10-22
CPC分类号： G06F15/8053
摘要： A receiver circuit has a chain of stream processing circuits (10a-c)—having control parameter inputs for receiving control parameter values. To facilitate design of circuits that receive data with a variable block size, an included control circuit (14) selects block sizes of blocks of samples in the respective streams of a plurality of the stream processing circuits (10a-c), a control parameter value for each particular block. The control circuit transmits instructions specifying the selected block sizes and control parameter values to local control circuits (11). Each local control circuit is coupled to the control circuit (14) and the control input of a respective corresponding stream processing circuit (10a-c). Each local control circuit (11) receives at least part of the instructions and applies parameter values from the instructions to its corresponding stream processing circuit (10a-c). The local control circuit (11) controls timing of control parameter updates using block sizes from the instructions.
摘要翻译： 接收器电路具有一串流处理电路（10a-c） - 具有用于接收控制参数值的控制参数输入。 为了便于以可变块大小接收数据的电路的设计，所附的控制电路（14）选择多个流处理电路（10a-c）的各个流中的采样块的块大小，控制参数值 对于每个特定块。 控制电路向本地控制电路（11）发送指定所选择的块大小和控制参数值的指令。 每个本地控制电路耦合到控制电路（14）和相应的对应流处理电路（10a-c）的控制输入。 每个本地控制电路（11）接收至少部分指令，并将参数值从指令应用到其相应的流处理电路（10a-c）。 本地控制电路（11）使用来自指令的块大小控制控制参数更新的定时。
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8.发明授权公开(公告)号：US06772183B1
公开(公告)日：2004-08-03
申请号：US09287163
申请日：1999-04-06
IPC分类号： G06F1714
CPC分类号： G06F17/14
摘要： The device for converting series of A input data elements to series of A output data elements comprises a memory means (110) for containing these series of input and output data elements. The device further includes at least two converters (112, 114) which are arranged parallel to each other and which are used to convert B input data elements to B output data elements, where A is greater than B.
摘要翻译： 用于将A个输入数据元素的系列转换为A个输出数据元素的装置包括用于存储这些一系列输入和输出数据元素的存储装置（110）。 该装置还包括至少两个彼此平行配置的转换器（112,114），用于将B个输入数据元素转换为B个输出数据元素，其中A大于B
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