公开(公告)号：US20240212728A1

公开(公告)日：2024-06-27

申请号：US18145927

申请日：2022-12-23

申请人： Integrated Silicon Solution Inc.

发明人： Jeong Ho BANG ,  Hyeon Jae LEE ,  Wol Jin LEE ,  Ki Hyung RYOO ,  Kwang Rae CHO ,  Sun Byeong YOON

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C8/18

CPC分类号： G11C7/109 ,  G11C7/1087 ,  G11C7/12 ,  G11C8/18

摘要： A memory core characteristic screening method includes the following steps. A command signal transmitting step includes configuring a processing module to transmit a command signal to a memory device. A first internal operating step includes configuring the memory device to operate a first operation to one of a word line, a bit line pair and a column line after a first strobe signal delay time according to a first command. A second internal operating step includes configuring the memory device to operate a second operation to another one of the word line, the bit line pair and the column line after a second strobe signal delay time according to a second command. A memory core characteristic screening step includes screening a memory core characteristic by shorting a timing between the first strobe signal delay time and the second strobe signal delay time.

公开(公告)号：US20240274214A1

公开(公告)日：2024-08-15

申请号：US18168628

申请日：2023-02-14

申请人： Integrated Silicon Solution Inc.

发明人： Hyeon Jae LEE ,  Jeong Ho BANG ,  Wol Jin LEE ,  Ki Hyung RYOO ,  Kwang Rae CHO ,  Sun Byeong YOON

IPC分类号： G11C29/12 ,  G11C29/36

CPC分类号： G11C29/12015 ,  G11C29/1201 ,  G11C29/36 ,  G11C2029/3602

摘要： A memory interface circuitry includes a clock generator to convert the first clock signal into a second clock signal, a state machine to generate a test signal according to the second clock signal, a data pattern generator to generate a plurality of pre-defined data, a read register to sequentially output the plurality of pre-defined data, an I/O interface to capture a plurality of data from the plurality of pre-defined data according to a write strobe signal, a write register to receive and store the plurality of data from the I/O interface, and a comparator to compare the plurality of pre-defined data with the plurality of data to generate a test result. The test result is configured to verify an operation of the I/O interface.